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AR# 7262

FPGA Express: Is there an option to disable carry logic?

説明

Keywords: FPGA Express, Foundation, VHDL, Verilog, carry, arithmetic

Urgency: Standard

General Description:
Is there an option to disable carry logic when synthesizing HDL for XC4000, Spartan
and Virtex architectures?

ソリューション

There is no way to disable the inference of carry logic when synthesizing arithmetic
functions using FPGA Express. As long as arithmetic operators are used in your HDL
code, carry logic will be inferred.
AR# 7262
作成日 08/31/2007
最終更新日 10/03/2008
ステータス アーカイブ
タイプ 一般