AR# 72923

2019.2 Vivado IP Release Notes - All IP Change Log Information

説明

This Answer Record contains a comprehensive list of IP change log information from Vivado 2019.2 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

ソリューション

(c) Copyright 2019 Xilinx, Inc.

All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith.

Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications").

Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.


100G Multirate Ethernet MAC (MRMAC) (1.1)

* Version 1.1

* Feature Enhancement: 4x10GE core speed support

* Feature Enhancement: 2x50GE core speed support

* Feature Enhancement: 1x40GE core speed support

* Revision change in one or more subcores


100M/1G TSN Subsystem (2.0)

* Version 2.0 (Rev. 4)

* General: No updates. No Functional changes

* Revision change in one or more subcores


10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 7)

* No changes


10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 16)

* Revision change in one or more subcores


10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 12)

* Revision change in one or more subcores


10G/25G Ethernet Subsystem (3.1)

* Version 3.1

* Bug Fix: Updated default values for txoutclksel and rxoutclksel for UltraScale and UltraScale plus

* Bug Fix: Updated Versal example design for optimal usage of BUFG_GT

* Feature Enhancement: Added drp_rst for UltraScale+

* Feature Enhancement: Added QPLL0RESET port access provided

* Feature Enhancement: Removed shared logic tab and GT selections for Versal parts

* Feature Enhancement: Updated reset structure for Versal family with reset_ip

* Revision change in one or more subcores


1G/10G/25G Switching Ethernet Subsystem (2.4)

* Version 2.4

* Port Change: Added stat_tx_unicast, stat_tx_multicast, stat_tx_broadcast, stat_tx_vlan, stat_rx_unicast, stat_rx_multicast, stat_rx_broadcast, stat_rx_vlan, stat_rx_inrangeerr ports for 32bit MAC+PCS/PMA core configuration

* Bug Fix: Updated for TIMING DRCs

* Bug Fix: Fixed CDC's

* Other: added new devices support

* Revision change in one or more subcores


1G/2.5G Ethernet PCS/PMA or SGMII (16.1)

* Version 16.1 (Rev. 7)

* Bug Fix: Fixed for TIMINGs DRCs and CDCs

* Revision change in one or more subcores


32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 12)

* No changes


3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 17)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 16)

* General: polarity of CE changed in metadata. No change to functionality.


3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 15)

* General: polarity of CE changed in metadata. No change to functionality.


3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 19)

* Bug Fix: Device support Versal fix. No change to functionality.


3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 16)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 16)

* General: polarity of CE changed in metadata. No change to functionality.


40G/50G Ethernet Subsystem (3.0)

* Version 3.0

* Feature Enhancement: Added Versal GTWIZ support

* Revision change in one or more subcores


64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 11)

* No changes


7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 11)

* No changes


7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 11)

* No changes


AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 15)

* Revision change in one or more subcores


AI Engine (1.0)

* Version 1.0

* No changes


AMM Master Bridge (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores


AMM Slave Bridge (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores


AXI 1G/2.5G Ethernet Subsystem (7.1)

* Version 7.1 (Rev. 7)

* Feature Enhancement: BRAM moved to XPM Memory - No functional changes

* Other: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core

* Revision change in one or more subcores


AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 17)

* Revision change in one or more subcores


AXI APB Bridge (3.0)

* Version 3.0 (Rev. 16)

* General: Fixed minor issues in example design of the IP


AXI BRAM Controller (4.1)

* Version 4.1 (Rev. 2)

* Bug Fix: BRAM address in full_axi module is not driving properly for dual port ECC configurations. This issue is fixed.


AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 10)

* General: Users can now optionally access powerdown signals from their user logic in UltraScale PCIe mode.

* Revision change in one or more subcores


AXI CAN (5.0)

* Version 5.0 (Rev. 23)

* Revision change in one or more subcores


AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 20)

* Revision change in one or more subcores


AXI Chip2Chip Bridge (5.0)

* Version 5.0 (Rev. 7)

* Revision change in one or more subcores


AXI Clock Converter (2.1)

* Version 2.1 (Rev. 19)

* General: Added XDC LUTAR-1 waiver

* Revision change in one or more subcores


AXI Crossbar (2.1)

* Version 2.1 (Rev. 21)

* General: Generate BD error when attempting to program more than 16 decode slots

* Revision change in one or more subcores


AXI Data FIFO (2.1)

* Version 2.1 (Rev. 19)

* General: Added XDC waiver file

* Revision change in one or more subcores


AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 20)

* Revision change in one or more subcores


AXI DataMover (5.1)

* Version 5.1 (Rev. 22)

* Revision change in one or more subcores


AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 21)

* General: enhanced support for IP Integrator

* Revision change in one or more subcores


AXI EMC (3.0)

* Version 3.0 (Rev. 20)

* Revision change in one or more subcores


AXI EPC (2.0)

* Version 2.0 (Rev. 23)

* Revision change in one or more subcores


AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 21)

* Feature Enhancement: BRAM moved to XPM Memory - No functional changes


AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes


AXI Ethernet Lite (3.0)

* Version 3.0 (Rev. 18)

* General: Added Versal devices support

* Revision change in one or more subcores


AXI GPIO (2.0)

* Version 2.0 (Rev. 22)

* General: No Functional changes

* Revision change in one or more subcores


AXI HB ICAP (1.0)

* Version 1.0

* General: Initial release


AXI HWICAP (3.0)

* Version 3.0 (Rev. 24)

* General: minor RTL updates. No Functional changes

* Revision change in one or more subcores


AXI IIC (2.0)

* Version 2.0 (Rev. 23)

* General: No Functional changes

* Revision change in one or more subcores


AXI Interconnect (2.1)

* Version 2.1 (Rev. 21)

* Revision change in one or more subcores


AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 14)

* Bug Fix: Handle IVAR reset values greater than 32 bits correctly on Windows


AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes


AXI MMU (2.1)

* Version 2.1 (Rev. 18)

* Revision change in one or more subcores


AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes


AXI Memory Init (1.0)

* Version 1.0 (Rev. 1)

* General: Supports non-zero DATA value configurable by user parameter

* Revision change in one or more subcores


AXI Memory Mapped To PCI Express (2.9)

* Version 2.9 (Rev. 2)

* Revision change in one or more subcores


AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 19)

* Revision change in one or more subcores


AXI Multi Channel Direct Memory Access (1.1)

* Version 1.1 (Rev. 1)

* General: Bug Fix

* Revision change in one or more subcores


AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 22)

* General: updated trace mode log to get addr and length on AXIS_TDATA

* Revision change in one or more subcores


AXI Protocol Checker (2.0)

* Version 2.0 (Rev. 6)

* General: Disable Exclusive access check

* Revision change in one or more subcores


AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 20)

* Revision change in one or more subcores


AXI Protocol Firewall (1.0)

* Version 1.0 (Rev. 8)

* General: Clean up names of fields in MI_Soft_Fault_Control register.

* Revision change in one or more subcores


AXI Quad SPI (3.2)

* Version 3.2 (Rev. 19)

* General: Internal GUI changes and New commands support for Micron and adding Macronix feature.

* Revision change in one or more subcores


AXI Register Slice (2.1)

* Version 2.1 (Rev. 20)

* General: Added reserved modes for internal use.

* General: Added CDC-7 waiver to XDC.

* Revision change in one or more subcores


AXI Sideband Utility (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores


AXI SmartConnect (1.0)

* Version 1.0 (Rev. 12)

* Feature Enhancement: Reduce area for AXI4/AXI3-to-AXI4-Lite protocol conversion when all MI are AXI4-Lite

* Feature Enhancement: SystemC model for AXI4-Lite transfers

* Revision change in one or more subcores


AXI TFT Controller (2.0)

* Version 2.0 (Rev. 23)

* Revision change in one or more subcores


AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 12)

* Revision change in one or more subcores


AXI Timer (2.0)

* Version 2.0 (Rev. 22)

* General: No Functional changes

* Revision change in one or more subcores


AXI Traffic Generator (3.0)

* Version 3.0 (Rev. 6)

* General: Fixed GUI in STRMG mode

* General: Minor Bug fixes

* Revision change in one or more subcores


AXI UART16550 (2.0)

* Version 2.0 (Rev. 22)

* General: SIM_DEVICE updated for Versal.

* Revision change in one or more subcores


AXI USB2 Device (5.0)

* Version 5.0 (Rev. 21)

* Revision change in one or more subcores


AXI UART Lite (2.0)

* Version 2.0 (Rev. 24)

* General: No Functional changes

* Revision change in one or more subcores


AXI Verification IP (1.1)

* Version 1.1 (Rev. 6)

* Revision change in one or more subcores


AXI Video Direct Memory Access (6.3)

* Version 6.3 (Rev. 8)

* Revision change in one or more subcores


AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 22)

* Revision change in one or more subcores


AXI-Stream FIFO (4.2)

* Version 4.2 (Rev. 2)

* Feature Enhancement: CASCADE_HEIGHT parameter added for TX and RX FIFOs

* Revision change in one or more subcores


AXI4 Debug Hub (1.0)

* Version 1.0

* No changes


AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 16)

* General: Waivers updated in the constraints file. No functional changes


AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 19)

* General: Initialize registers to default value

* Revision change in one or more subcores


AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 21)

* Revision change in one or more subcores


AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 18)

* General: Initialize registers to default value

* Revision change in one or more subcores


AXI4-Stream Data FIFO (2.0)

* Version 2.0 (Rev. 2)

* Revision change in one or more subcores


AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 19)

* General: Allow 1:1 converter mode (pass-through)

* Revision change in one or more subcores


AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 21)

* Revision change in one or more subcores


AXI4-Stream Protocol Checker (2.0)

* Version 2.0 (Rev. 4)

* Revision change in one or more subcores


AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 20)

* General: Added reserved modes for internal use.

* Revision change in one or more subcores


AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 20)

* General: Initialize registers to default value

* Revision change in one or more subcores


AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 20)

* Revision change in one or more subcores


AXI4-Stream Verification IP (1.1)

* Version 1.1 (Rev. 6)

* Revision change in one or more subcores


AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 10)

* No changes


Accumulator (12.0)

* Version 12.0 (Rev. 14)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


Adder/Subtracter (12.0)

* Version 12.0 (Rev. 14)

* General: polarity of CE changed in metadata. No change to functionality.


Advanced IO Wizard (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores


Audio Clock Recovery Unit (1.0)

* Version 1.0 (Rev. 1)

* No changes


Audio Formatter (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


Aurora 64B66B (12.0)

* Version 12.0 (Rev. 1)

* General: Updated loopback port connections in example design for Generate Aurora without GT option for TX/RX Simplex cases

* Revision change in one or more subcores


Aurora 8B10B (11.1)

* Version 11.1 (Rev. 8)

* Revision change in one or more subcores


Binary Counter (12.0)

* Version 12.0 (Rev. 14)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


Block Memory Generator (8.4)

* Version 8.4 (Rev. 4)

* Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations


CANFD (2.0)

* Version 2.0 (Rev. 2)

* General: Updated Example Design clocking topology for Versal devices

* Revision change in one or more subcores


CIC Compiler (4.0)

* Version 4.0 (Rev. 15)

* General: changing polarity of CE in metadata. No change to functionality.


CORDIC (6.0)

* Version 6.0 (Rev. 16)

* Bug Fix: Fix for C model memory leak in sin cos operation.

* Revision change in one or more subcores


CPRI (8.11)

* Version 8.11

* Port Change: Added Versal GT interface ports.

* Bug Fix: Fixed Critical Warning in IPI GMII interface associated with multiple clocks.

* Feature Enhancement: Added Versal support for all 64b66b line rates including FEC and 8b10b line rates between 9.8G & 2.4G.

* Feature Enhancement: Added QPLL display field to the CPRI GUI for 24.3G line rates. refclk0 must be used with QPLL0 and refclk1 with QPLL1.

* Feature Enhancement: Delayed CPLL power down de-assertion until cpll_reset is deasserted, stops CPLL calibration starting before reset is complete.

* Other: Implemented new IP waiver mechanism.

* Revision change in one or more subcores


Card Management Solution Subsystem (2.0)

* Version 2.0

* General: Simplified memory map reduced range to 128k

* General: Added demonstration testbench

* General: Added example design

* General: Added support for U50/U280 parts

* General: Added watchdog feature support

* Revision change in one or more subcores


Chroma Resampler (4.0)

* Version 4.0 (Rev. 14)

* No changes


Clock Verification IP (1.0)

* Version 1.0 (Rev. 2)

* No changes


Clocking Wizard (6.0)

* Version 6.0 (Rev. 4)

* Bug Fix: Internal GUI fixes

* Other: CR Fixes


Color Correction Matrix (6.0)

* Version 6.0 (Rev. 15)

* No changes


Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 14)

* No changes


Compact GT (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores


Complex Multiplier (6.0)

* Version 6.0 (Rev. 18)

* General: Comment changes only. No change to functionality

* Revision change in one or more subcores


Concat (2.1)

* Version 2.1 (Rev. 3)

* No changes


Constant (1.1)

* Version 1.1 (Rev. 6)

* No changes


Control, Interfaces & Processing System (1.0)

* Version 1.0

* No changes


Convolution Encoder (9.0)

* Version 9.0 (Rev. 15)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


DDR3 SDRAM (MIG) (1.4)

* Version 1.4 (Rev. 8)

* Revision change in one or more subcores


DDR4 SDRAM (MIG) (2.2)

* Version 2.2 (Rev. 8)

* General: Updated for 2019.2

* Revision change in one or more subcores


DDS Compiler (6.0)

* Version 6.0 (Rev. 19)

* Revision change in one or more subcores


DMA/Bridge Subsystem for PCI Express (PCIe) (4.1)

* Version 4.1 (Rev. 4)

* General: Added Tandem support for xcvu45p and xcvu47p devices.

* Revision change in one or more subcores


DP DSC AXI4-Stream to Video Out (1.0)

* Version 1.0

* Derived from v_axi4s_vid_out IP and have done updates needed to support DP DSC TX.


DSP Macro (1.0)

* Version 1.0

* New Feature: Squaring operations from the result of the preadder supported for UltraScale and Versal

* Other: Initial release of DSP Macro. This core supersedes DSP48 Macro (xbip_dsp48_macro).

* Other: Support for Versal devices (DSP58/DSP Engine)

* Other: Improved GUI error handling

* Other: Improved full precision output (P) width calculation. Preadder additions now increase full precision width appropriately.


DSP48 Macro (3.0)

* Version 3.0 (Rev. 17)

* No changes


DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 15)

* No changes


Debug Bridge (3.0)

* Version 3.0 (Rev. 5)

* No changes


Discrete Fourier Transform (4.1)

* Version 4.1 (Rev. 1)

* No changes


DisplayPort (9.0)

* Version 9.0 (Rev. 2)

* Revision change in one or more subcores


DisplayPort RX Subsystem (2.1)

* Version 2.1 (Rev. 6)

* Bug Fix: Added AXIS Slice after CRC checker in RX path

* Feature Enhancement: Allow change to IIC speed

* Revision change in one or more subcores


DisplayPort TX Subsystem (2.1)

* Version 2.1 (Rev. 6)

* Bug Fix: Added AXIS Slice after CRC checker in RX path

* Revision change in one or more subcores


Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 13)

* No changes


Divider Generator (5.1)

* Version 5.1 (Rev. 16)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


Double Data Rate Sampling (1.0)

* Version 1.0

* No changes


ECC (2.0)

* Version 2.0 (Rev. 13)

* No changes


ERNIC (1.0)

* Version 1.0 (Rev. 2)

* General: IP updated to improve Timing

* Revision change in one or more subcores


ETRNIC (1.1)

* Version 1.1 (Rev. 3)

* Revision change in one or more subcores


FEC 5G Common Utilities (1.1)

* Version 1.1 (Rev. 1)

* No changes


FIFO Generator (13.2)

* Version 13.2 (Rev. 5)

* General: IP Waivers update in constraint files. No functional changes

* Revision change in one or more subcores


FIR Compiler (7.2)

* Version 7.2 (Rev. 13)

* General: Improved efficiency to C model output. No change to functionality.


Fast Fourier Transform (9.1)

* Version 9.1 (Rev. 3)

* General: support for Versal devices. No change to functionality.

* Revision change in one or more subcores


Fibre Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 12)

* General: Added example design support for Versal devices.

* Revision change in one or more subcores


Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 10)

* No changes


FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 12)

* General: Added example design support for Versal devices.

* Revision change in one or more subcores


Floating-point (7.1)

* Version 7.1 (Rev. 9)

* General: initialization of internal signals to address benign warnings.

* Revision change in one or more subcores


G.709 FEC Encoder/Decoder (2.4)

* Version 2.4 (Rev. 2)

* Revision change in one or more subcores


G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 18)

* General: Fixed failure flag alignment issue.


G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 18)

* No changes


Gamma Correction (7.0)

* Version 7.0 (Rev. 15)

* No changes


Gamma LUT (1.0)

* Version 1.0 (Rev. 6)

* General: Updated example design software to support Vitis.

* Revision change in one or more subcores


GMII to RGMII (4.0)

* Version 4.0 (Rev. 7)

* No changes


HBM IP (1.0)

* Version 1.0 (Rev. 5)

* General: Added support for 8H parts

* General: Update GUI options for Parity. Added option for User (AXI) parity

* General: Updated synthesizable example design for running continuous traffic

* General: Fixed calibration issue for low frequency

* General: Added GUI option to disable Hardware Debug tool.

* General: Updated constraint for example design


HDCP (1.0)

* Version 1.0 (Rev. 3)

* No changes


HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 3)

* No changes


HDCP 2.2 Cipher for DP (1.0)

* Version 1.0

* No changes


HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0 (Rev. 2)

* No changes


HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes


HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 12)

* Revision change in one or more subcores


HDCP 2.2 Receiver for DisplayPort 1.4 Subsystems (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores


HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 12)

* Revision change in one or more subcores


HDCP 2.2 Transmitter for DisplayPort 1.4 Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores


HDMI 1.4/2.0 Receiver (3.0)

* Version 1.1

* No changes


HDMI 1.4/2.0 Receiver Subsystem (3.1)

* Version 3.1 (Rev. 3)

* Bug Fix: Fixed Aligner Detection Issue

* Feature Enhancement: Added support for Arbitrary Resolution

* Revision change in one or more subcores


HDMI 1.4/2.0 Transmitter (3.0)

* Version 2.0

* No changes


HDMI 1.4/2.0 Transmitter Subsystem (3.1)

* Version 3.1 (Rev. 3)

* Bug Fix: Fixed Audio Sampling Frequency = 768*Fs for I2S Example Design

* Feature Enhancement: Added support for Arbitrary Resolution

* Feature Enhancement: Change oversampling rate support x4 to x2 for Versal

* Revision change in one or more subcores


HDMI GT Controller (1.0)

* Version 1.0 (Rev. 1)

* General: Block Automation enablement

* General: Updated SIM_DEVICE values in RTL

* General: Added C_DRU_Refclk_Freq_MHz

* General: Restructured POR handling


High Speed SelectIO Wizard (3.5)

* Version 3.5 (Rev. 2)

* General: Internal Bug fixes.


I2S Receiver (1.0)

* Version 1.0 (Rev. 3)

* No changes


I2S Transmitter (1.0)

* Version 1.0 (Rev. 3)

* No changes


IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 18)

* No changes


IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 18)

* No changes


IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 18)

* No changes


IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 18)

* Revision change in one or more subcores


IBERT UltraScale GTH (1.4)

* Version 1.4 (Rev. 3)

* Bug Fix: Fixed issue which was causing incorrect BUFGCE loc for DMON clock

* Revision change in one or more subcores


IBERT UltraScale GTM (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Fixed issue which was causing the channel 1 of each dual with FEC mode failure

* Revision change in one or more subcores


IBERT UltraScale GTY (1.3)

* Version 1.3 (Rev. 3)

* Revision change in one or more subcores


IEEE 802.3 200G RS-FEC (1.0)

* Version 1.0 (Rev. 8)

* General: Device support expanded to include Alveo

* Revision change in one or more subcores


IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 14)

* General: Added example design support for Versal devices.

* Revision change in one or more subcores


IEEE 802.3 400G RS-FEC (1.0)

* Version 1.0 (Rev. 8)

* General: Device support expanded to include Alveo

* Revision change in one or more subcores


IEEE 802.3 50G RS-FEC (2.0)

* Version 2.0 (Rev. 2)

* General: Added example design support for Versal devices.

* General: Added fec_enable port in KP4 (this port was only present in KR4). It is used to enable or bypass the core

* Revision change in one or more subcores


IEEE 802.3 Clause 74 FEC (1.0)

* Version 1.0 (Rev. 5)

* General: Added example design support for Versal devices.

* Revision change in one or more subcores


IEEE 802.3 Multi-channel 25G RSFEC (1.0)

* Version 1.0 (Rev. 6)

* General: Updated cmac_usplus version number

* General: Resolved Questa encrypted simulation issue


IEEE 802.3bj 100G RS-FEC (2.0)

* Version 2.0 (Rev. 6)

* General: Added example design support for Versal devices.

* Revision change in one or more subcores


ILA (Integrated Logic Analyzer with AXIS Interface) (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Added Interface_Monitor and Mixed mode debug support

* Revision change in one or more subcores


ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 10)

* General: Updated the waivers for CDC

* Revision change in one or more subcores


IOModule (3.1)

* Version 3.1 (Rev. 5)

* Bug Fix: Calculate address and mask parameters greater than 32 bits correctly on Windows

* Bug Fix: Ensure that register names follow IP-XACT standard

* Other: Added reset on all flip-flops, no functional changes


Image Enhancement (8.0)

* Version 8.0 (Rev. 15)

* No changes


In System IBERT (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores


Interlaken 150G (2.4)

* Version 2.4 (Rev. 4)

* Bug Fix: Updated Board Tab visibility for VCU108 board

* Revision change in one or more subcores


Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 15)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


JESD204 (7.2)

* Version 7.2 (Rev. 7)

* Revision change in one or more subcores


JESD204 PHY (4.0)

* Version 4.0 (Rev. 7)

* Bug Fix: NA.

* Feature Enhancement: Added support for new devices.

* Other: NA

* Revision change in one or more subcores


JESD204C (4.2)

* Version 4.2

* Bug Fix: STAT_RESET correctly reports CTRL_RESET

* Feature Enhancement: Added support Versal GTY

* Feature Enhancement: Added support for new UltraScale+ devices

* Feature Enhancement: Enhanced example design for reuse of gen/chk path in custom designs

* Other: None

* Revision change in one or more subcores


JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 10)

* General: IP Constraints update to set used_in to opt_design_post

* Revision change in one or more subcores


LDPC Encoder/Decoder (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Correction dump_block function in C model example application for 5G configurations.

* Bug Fix: Update to C model example application dump_axis function to support MS Visual Studio.

* Bug Fix: Enhanced LDPC code validation.

* Other: Update PS example design to use Vitis.


LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 17)

* Bug Fix: Calculate address and mask parameters greater than 32 bits correctly on Windows

* Bug Fix: Ensure that register names follow IP-XACT standard

* Other: Added reset on all flip-flops, no functional changes


LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores


LTE DL Channel Encoder (4.0)

* Version 4.0 (Rev. 1)

* General: Revision level update to prevent loss of data in segmented transport block

* General: C-model update to expand scope of helper function which converts LTE configuration into core's memory writes. Function can now cope with layer mapping of 1:4.

* Revision change in one or more subcores


LTE Fast Fourier Transform (2.1)

* Version 2.1 (Rev. 1)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores


LTE RACH Detector (3.1)

* Version 3.1 (Rev. 6)

* General: Code tidy-up. No change to functionality.

* Revision change in one or more subcores


LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 16)

* No changes


Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 10)

* Feature Enhancement: Added protocol option for frequency optimization


MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 8)

* No changes


MIPI CSI-2 Rx Subsystem (4.1)

* Version 4.1

* New Feature: Added additional parameter to disable register interface, this improves resource count

* Feature Enhancement: Added MIPI D-PHY v2.0 Specification support and 2.5Gbps line rate support

* Other: Added SP701 based Example Design support

* Revision change in one or more subcores


MIPI CSI-2 Tx Controller (1.0)

* Version 1.0 (Rev. 4)

* No changes


MIPI CSI-2 Tx Subsystem (2.0)

* Version 2.0 (Rev. 7)

* Feature Enhancement: Added MIPI D-PHY v2.0 Specification support with limited line-rate support

* Other: Added support for Versal devices

* Revision change in one or more subcores


MIPI D-PHY (4.1)

* Version 4.1 (Rev. 5)

* New Feature: MIPI D-PHY Splitter Bridge mode added. Allows user to replicate incoming MIPI stream on to multiple output MIPI streams

* Feature Enhancement: Added MIPI D-PHY v2.0 Specification support with limited line-rate support

* Revision change in one or more subcores


MIPI DSI TX Controller (1.0)

* Version 1.0 (Rev. 7)

* No changes


MIPI DSI TX Subsystem (2.0)

* Version 2.0 (Rev. 7)

* New Feature: Added DCS long packet support

* Feature Enhancement: Added MIPI D-PHY v2.0 specification support with limited line-rate as early access

* Revision change in one or more subcores


Mailbox (2.1)

* Version 2.1 (Rev. 12)

* Bug Fix: Ensure that register names follow IP-XACT standard


Mammoth Transcoder (1.0)

* Version 1.0

* No changes


Memory Helper Core (1.4)

* Version 1.4

* No changes


Memory Interface Generator (MIG 7 Series) (4.2)

* Version 4.2 (Rev. 1)

* No changes


MicroBlaze (11.0)

* Version 11.0 (Rev. 2)

* Bug Fix: Ensure that swapb and swaph instruction result is correct. Versions that have this issue: 11.0, 11.0 (Rev. 1). Can only occur with area optimization when reorder instructions are enabled and pattern compare instructions are not enabled.

* Bug Fix: Do not generate underflow for corner case double multiplication 2.225073858507202e-308 * 0.9999999999999998. Versions that have this issue: 11.0, 11.0 (Rev. 1). Can only occur with 64-bit mode when floating point is enabled.

* Bug Fix: Calculate address parameters greater than 32 bits correctly on Windows. Versions that have this issue: 9.6, 10.0, 11.0, 11.0 (Rev. 1). Can only occur with extended address enabled on Windows Operating System.

* Feature Enhancement: Added additional 64-bit immediate arithmetic and logic instructions

* Other: Versal ACAP Series architecture support added

* Other: Added reset on all flip-flops, no functional changes

* Other: Changed default value of parameters C_ICACHE_ALWAYS_USED and C_DCACHE_ALWAYS_USED to 1

* Other: Corrected Vivado configuration dialog branch target cache size tooltip, choices and Block RAM count


MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 17)

* Bug Fix: Ensure that register names follow IP-XACT standard

* Other: Updated to add support for Versal BSCAN

* Other: Added reset on all flip-flops, no functional changes

* Other: Updated constraint for placing internal BSCAN in master SLR

* Other: Improved internal BSCAN hold timing


MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 12)

* Feature Enhancement: Added support for external BSCAN

* Feature Enhancement: Added support for AXI parallel debug

* Revision change in one or more subcores


Multiplier (12.0)

* Version 12.0 (Rev. 16)

* General: Support for Versal devices


Multiply Adder (3.0)

* Version 3.0 (Rev. 15)

* General: warning suppression. No change to functionality

* Revision change in one or more subcores


Mutex (2.1)

* Version 2.1 (Rev. 11)

* Bug Fix: Ensure that register names follow IP-XACT standard


NVMe Host Accelerator (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Timing fixes for issues

* Feature Enhancement: Tested with multiple SSDs for interoperability testing

* Revision change in one or more subcores


NoC Clock Re-Convergent Buffer (1.0)

* Version 1.0

* No changes


NoC NIDB (1.0)

* Version 1.0

* No changes


NoC Packet Switch (1.0)

* Version 1.0

* No changes


PCIE DMA Subsystem for VERSAL (1.0)

* Version 1.0

* General: Initial release


PCIe AXI4-Lite_Tap (1.0)

* Version 1.0

* New Feature: Native Vivado Release

* New Feature: Initial release.

* New Feature: Hidden IP; no user docs.


PCIe PHY IP (1.0)

* Version 1.0 (Rev. 12)

* Bug Fix: Set PHY_SIM_EN as TRUE for faster simulation

* Revision change in one or more subcores


PR AXI Shutdown Manager (1.0)

* Version 1.0 (Rev. 1)

* No changes


PR Bitstream Monitor (1.0)

* Version 1.0 (Rev. 1)

* No changes


Partial Reconfiguration Controller (1.3)

* Version 1.3 (Rev. 3)

* General: Added a memory map to the AXIMM interface. This is required to work with the SmartConnect

* Revision change in one or more subcores


Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 8)

* General: Fixed the default width of AXIMM WSTRB to match the data width


Peak Cancellation Crest Factor Reduction (6.3)

* Version 6.3 (Rev. 1)

* Feature Enhancement: Fmax improvement for CPS=2 for both SPP and Non-SPP modes


Polar Encoder/Decoder (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Allowing PS based example design for encoder configurations

* Other: Update PS based example design to use Vitis.


Processor System Reset (5.0)

* Version 5.0 (Rev. 13)

* No changes


QDRII+ SRAM (MIG) (1.4)

* Version 1.4 (Rev. 8)

* General: Updated for 2019.2

* Revision change in one or more subcores


QDRIV SRAM (MIG) (2.0)

* Version 2.0 (Rev. 8)

* Revision change in one or more subcores


QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes


QSGMII (3.4)

* Version 3.4 (Rev. 7)

* General: Support for Zynq UltraScale+ devices

* Revision change in one or more subcores


Queue DMA Subsystem for PCI Express (PCIe) (3.0)

* Version 3.0 (Rev. 3)

* Bug Fix: Fixed the connection of signal cfg_flr_in_process from PCIE4 to QDMA

* Feature Enhancement: Added CONFIG.no_uram {true} TCL option to not use URAM

* Feature Enhancement: Added Resizable BAR support with TCL option CONFIG.rbar_enable {true}

* Feature Enhancement: Resource reduction changes in RTL for some configurations

* Revision change in one or more subcores


RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 14)

* General: polarity of CE changed in metadata. No change to functionality.


RAMA IP (1.1)

* Version 1.1 (Rev. 3)

* General: Updated example design to support new devices (xcvu45p & xcvu47p).

* Revision change in one or more subcores


RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 13)

* No changes


RLDRAM3 (MIG) (1.4)

* Version 1.4 (Rev. 8)

* Revision change in one or more subcores


Radio over Ethernet Framer (2.1)

* Version 2.1

* Bug Fix: Oran_Mode=0   : Fixed issues affecting packet push-back on framer AXI-Stream input interface: tready is de-asserted when the framer is disabled or if the corresponding input FIFO gets almost full

* Bug Fix: Oran_Mode=5   : Bug fixes and cycle reductions in various CTRL path state machines

* Bug Fix: Oran_Mode=5   : Fix registering of parameters at symbol rollover in DL Data path

* Bug Fix: Oran_Mode=5   : Fixed a bug in the UL Ethernet packet encapsulator which was generating partially wrong packets when extracting data from more than one Spatial Stream

* Bug Fix: Oran_Mode=5   : Fixed a bug in the DL Ethernet packet filter which was the loss one packet when many short control packets were being received in sequence

* Bug Fix: Oran_Mode=0|5 : Fixes to limit removal of some signals in Example Design, to allow post-implementation simulation of Example Design to work

* Feature Enhancement: Oran_Mode=0   : Updated buffer manager in time domain application. The allowed values of 'Number of Ethernet packets to buffer' are 1, 2 and 3.

* Feature Enhancement: Oran_Mode=0   : Changed behavior of buffer manager in time domain. Once started, both read and write pointers are incremented automatically. If a slot has not been received an equivalent number of zero words are generated.

* Feature Enhancement: Oran_Mode=0   : Time domain buffer manager changed behavior: introduced the limitation that the chosen fixed Ethernet packet length in DL has to be multiple of 16 bytes

* Feature Enhancement: Oran_Mode=0   : Changed behavior of buffer manager in frequency domain. The allowed values of 'Number of Ethernet packets to buffer' are 0, 1 and 2.

* Feature Enhancement: Oran_Mode=0   : In order to allow managing out of order packets in frequency domain, a packet is generated only when there are more than 'Number of Ethernet packets to buffer' stored.

* Feature Enhancement: Oran_Mode=0   : Underflow is asserted when the read pointer comes across a slot which wasn't written; overflow is asserted if all the buffer's slots are full and a new packet is being received

* Feature Enhancement: Oran_Mode=0   : Optimization of the polling function to deal with situations of un-even traffic or when just one antenna is working

* Feature Enhancement: Oran_Mode=0   : Introduced full support for short packets as CTRL messages (Ethernet packets resulting in a length not supported by the IEEE 802.1 std are now padded by the framer and pad bytes are removed by the filter).

* Feature Enhancement: Oran_Mode=0   : Improved limitations on packets' length, data packets may carry 80 to 8118 bytes, control payloads may be 1 to 8118 bytes.

* Feature Enhancement: Oran_Mode=0   : Introduced auto-recovery capability of the deframer when the input FIFO becomes full due to un-expected issues on the Ethernet network.

* Feature Enhancement: Oran_Mode=5   : Enhancements to aid timing closure

* Feature Enhancement: Oran_Mode=5   : Addition of parameter Xran_Max_Dl_Sect_Per_Symbol to define the number of ORAN sections per symbol in Downlink.

* Feature Enhancement: Oran_Mode=5   : Addition of parameter Xran_Max_Ul_Sect_Per_Symbol to define the number of ORAN sections per symbol in Uplink.

* Feature Enhancement: Oran_Mode=5   : Unsolicited framer ports to support SRS with new parameter Xran_Unsol_Ports_Fram

* Feature Enhancement: Oran_Mode=0|5 : Early Beta support for Versal devices

* Other: None


Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 17)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 16)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


Reset Verification IP (1.0)

* Version 1.0 (Rev. 3)

* No changes


SC EXIT (1.0)

* Version 1.0 (Rev. 9)

* Feature Enhancement: Improve speed and reduce size of burst-to-singles splitting for AXI4-Lite MI.


SC MMU (1.0)

* Version 1.0 (Rev. 8)

* Feature Enhancement: Reduce area for AXI4/AXI3-to-AXI4Lite protocol conversion when all MI are AXI4Lite.


SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 9)

* Feature Enhancement: Reduce area for AXI4/AXI3-to-AXI4Lite protocol conversion when all MI are AXI4Lite.


SC SPLITTER (1.0)

* Version 1.0 (Rev. 4)

* No changes


SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 8)

* No changes


SDI RX to Video Bridge (2.0)

* Version 2.0

* No changes


SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* No changes


SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 7)

* No changes


SMPTE UHD-SDI RX (1.0)

* Version 1.0

* No changes


SMPTE UHD-SDI RX SUBSYSTEM (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Added CDC register to the QPLL Lock signal

* Bug Fix: Extended crc_err signal until next SAV

* Bug Fix: Updated UHDSDI-GT to support CPLL QPLL combo

* Bug Fix: Updated KCU116 example design with CPLL QPLL combo

* Bug Fix: Updated SDI SS to support YUV444 color format

* Bug Fix: Updated example design to use the latest psu_init.tcl

* Bug Fix: Updated example design software to support Vitis


SMPTE UHD-SDI TX (1.0)

* Version 1.0

* No changes


SMPTE UHD-SDI TX SUBSYSTEM (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Updated UHD-SDI GT for CPLL QPLL combo

* Bug Fix: Updated UHD-SDI GT ports for PICXO and FRACXO on both GTH and GTY

* Bug Fix: Fixed device selection for XCKU15P and XCVU35P

* Bug Fix: Updated SDI SS to support YUV444 color format

* Bug Fix: Updated example design software to support Vitis

* Revision change in one or more subcores


SPDIF/AES3 (2.0)

* Version 2.0 (Rev. 22)

* Revision change in one or more subcores


SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 14)

* General: Internal bug fixes.


Sensor Demosaic (1.0)

* Version 1.0 (Rev. 6)

* General: Updated example design software to support Vitis.

* Revision change in one or more subcores


Serial RapidIO Gen2 (4.1)

* Version 4.1 (Rev. 7)

* Revision change in one or more subcores


Shell Card Management Controller Subsystem (2.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores


Shell Utility MSP432 BSL CRC Generator (1.0)

* Version 1.0

* No changes


Slice (1.0)

* Version 1.0 (Rev. 2)

* No changes


SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 7)

* No changes


SmartConnect Node (1.0)

* Version 1.0 (Rev. 10)

* No changes


SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 7)

* No changes


SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 6)

* No changes


Soft ECC Proxy (1.0)

* Version 1.0

* No changes


Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 12)

* No changes


Soft-Decision FEC (1.1)

* Version 1.1 (Rev. 4)

* Bug Fix: Correction dump_block function in C model example application for 5G configurations.

* Bug Fix: Update to C model example application dump_axis function to support MS Visual Studio.

* Bug Fix: Correction to example design AXI4-Stream 256-bit & 512-bit TKEEP annotation blocks.

* Bug Fix: Enhanced LDPC code validation.

* Other: Update PS example design to use Vitis.


Stream Traffic Manager (1.0)

* Version 1.0

* No changes


Switch Core Top (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores


System Cache (5.0)

* Version 5.0

* Port Change: Added Initialization port

* Bug Fix: Added workaround for IES simulator error

* Feature Enhancement: Increased supported cache size

* Feature Enhancement: Added fine-grained control over RAM utilization

* Other: Update of control interface, no longer backwards compatible


System ILA (1.1)

* Version 1.1 (Rev. 6)

* Revision change in one or more subcores


System Management Wizard (1.3)

* Version 1.3 (Rev. 11)

* General: Internal GUI DRC updates. No affect to the customers.


TMR Comparator (1.0)

* Version 1.0 (Rev. 3)

* General: Added reset on all flip-flops, no functional changes

* Revision change in one or more subcores


TMR Inject (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Calculate address and mask parameters greater than 32 bits correctly on Windows

* Other: Added reset on all flip-flops, no functional changes


TMR Manager (1.0)

* Version 1.0 (Rev. 5)

* Bug Fix: Calculate address and mask parameters greater than 32 bits correctly on Windows

* Other: Added reset on all flip-flops, no functional changes


TMR Soft Error Mitigation Interface (1.0)

* Version 1.0 (Rev. 10)

* Bug Fix: Corrected update of parameter C_HAS_ERROR_INJECTION

* Bug Fix: Ensure that register names follow IP-XACT standard

* Feature Enhancement: Added selection of FIFO size

* Revision change in one or more subcores


TMR Voter (1.0)

* Version 1.0 (Rev. 3)

* General: Added reset on all flip-flops, no functional changes


TSN Endpoint Block (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores


TSN Tri Mode Ethernet MAC (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores


Time-Aware DMA (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores


Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes


Trace S2MM (1.0)

* Version 1.0

* Asynchronous writes and reset


Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 15)

* General: Added Versal device support.

* Revision change in one or more subcores


UHD-SDI Audio (2.0)

* Version 2.0 (Rev. 1)

* No changes


UHD-SDI GT (2.0)

* Version 2.0 (Rev. 1)

* Revision change in one or more subcores


UHD-SDI Video Pattern Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes


URAM Read Back (1.0)

* Version 1.0

* Initial core release


UltraScale 100G Ethernet Subsystem (2.5)

* Version 2.5 (Rev. 2)

* Bug Fix: Fixed the stat_rx_aligned and other stat_rx signals visibility for AXIS user interface configuration

* Bug Fix: Updated the missing ANLT ctl ports with AXI4 lite config to the core

* Revision change in one or more subcores


UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)

* Version 4.4 (Rev. 6)

* Bug Fix: ACS control register reserved bits are made Read Only

* Bug Fix: Updated the time_out logic on cfg_ext* interface

* Revision change in one or more subcores


UltraScale FPGAs Transceivers Wizard (1.7)

* Version 1.7 (Rev. 7)

* Feature Enhancement: Adjusted UltraScale GTH specific attributes for TXPI related advanced use cases

* Other: Modified delay powergood for GTHE4/GTYE4 to use shift register based logic


UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 12)

* General: Added support for VU45P and VU47P


UltraScale+ 100G Ethernet Subsystem (3.0)

* Version 3.0

* Bug Fix: Updated the missing ANLT ctl ports with AXI4 lite config to the core

* Bug Fix: Updated the axis_tx and axis_rx interfaces for TX OTN interface enabled configuration

* Bug Fix: Updated the GT group selection for caui4 configuration for xcvu13p-flga2577 devices

* Feature Enhancement: Integrated the changes for the GTM subcore

* Other: Added new UltraScale+ devices support

* Revision change in one or more subcores


UltraScale+ PCI Express 4c Integrated Block (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: ACS control register reserved bits are made Read Only

* Bug Fix: Changed RBAR Capability register(BAR0) default value

* Bug Fix: Fixed Legacy Extended config space interface connection issue in example design

* Feature Enhancement: Added support for XCVU45P, XCVU47P, XCVU19P and Fastnet devices

* Revision change in one or more subcores


UltraScale+ PCI Express Integrated Block (1.3)

* Version 1.3 (Rev. 6)

* Bug Fix: ACS control register reserved bits are made Read Only

* Bug Fix: RBAR Capability register(BAR0) default value modified

* Bug Fix: Legacy Extended config space interface connections fixed

* Feature Enhancement: Added support to XCVU45P and  XCVU47P devices

* Feature Enhancement: Added dual quad support to KU15P

* Revision change in one or more subcores


Universal Serial XGMII Ethernet Subsystem (1.1)

* Version 1.1 (Rev. 1)

* Bug Fix: Added new device support

* Bug Fix: Fixed CDC violation on RX GT user reset

* Revision change in one or more subcores


Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 4)

* No changes


Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* No changes


VIO (Virtual Input/Output with AXIS Interface) (1.0)

* Version 1.0

* No changes


VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 19)

* No changes


Versal PCI Express Integrated Block (1.0)

* Version 1.0 (Rev. 1)

* General: PIPE stages enabled for BRAM

* Revision change in one or more subcores


Versal PCIe PHY IP (1.0)

* Version 1.0 (Rev. 1)

* General: PIPE stages enabled for PIPE data


Versal QDRIV SRAM (1.0)

* Version 1.0

* Initial QDRIV_PL public release


Versal Soft DDR4 Memory Controller (1.0)

* Version 1.0

* General: Updated for 2019.2


Versal Soft RLDRAM3 Memory Controller (1.0)

* Version 1.0 (Rev. 1)

* General: Updated for 2019.2

* Revision change in one or more subcores


Video AXI4S Remapper (1.0)

* Version 1.0 (Rev. 12)

* General: Made IP visible in catalog

* General: Added 8 ppc support

* General: Updated example design for 2019.2

* Revision change in one or more subcores


Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 14)

* General: Added 8 ppc support.

* Revision change in one or more subcores


Video Deinterlacer (5.0)

* Version 5.0 (Rev. 14)

* Revision change in one or more subcores


Video DisplayPort 1.4 RX Subsystem (2.1)

* Version 2.1 (Rev. 1)

* Bug Fix: Updates to RX_Video_to_AXI4_Bridge and DisplayPort core are done to fix timing in FEC and DSC data paths

* Bug Fix: DP sink side logic has been updated to fix issue with audio payload being wrongly detected as header and header being detected as payload

* Bug Fix: Updates in 0x109h DPCD reg to control speed for the IIC EDID interface

* Bug Fix: RX audio interface outputs driven to zero when VB-ID bit-4 is set to 1

* Bug Fix: Fixed the AUX defer issue for AUX-over-I2C EDID read transaction with MOT bit set

* New Feature: HDCP 1.3 repeater support

* Feature Enhancement: DP Sink Fallback Video Formats Enumeration DPCD Register Addition at 0x00020h

* Feature Enhancement: XPM_FIFO migration

* Feature Enhancement: Added HDCP2.2 support with example design

* Revision change in one or more subcores


Video DisplayPort 1.4 TX Subsystem (2.1)

* Version 2.1 (Rev. 1)

* Bug Fix: Update has been done in DP source side logic, to detect the HSYNC signal in vertical blanking to fix display issues with some monitors

* Feature Enhancement: XPM_FIFO migration

* Feature Enhancement: Added HDCP2.2 support with example design

* Revision change in one or more subcores


Video Frame Buffer Read (2.1)

* Version 2.1 (Rev. 3)

* General: Added compatibility for Vitis

* Revision change in one or more subcores


Video Frame Buffer Write (2.1)

* Version 2.1 (Rev. 3)

* General: Added compatibility for Vitis

* Revision change in one or more subcores


Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores


Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores


Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 9)

* No changes


Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores


Video Mixer (4.0)

* Version 4.0 (Rev. 1)

* General: Added compatibility for Vitis

* Revision change in one or more subcores


Video Multi-Scaler (1.0)

* Version 1.0 (Rev. 2)

* General: Added compatibility with Vitis


Video On Screen Display (6.0)

* Version 6.0 (Rev. 16)

* No changes


Video PHY Controller (2.2)

* Version 2.2 (Rev. 4)

* Bug Fix: Fixed TMDS Clock pattern generator at 2PPC config

* Other: Added xcvu45 and xcvu47 devices

* Other: Changed Virtex HBM & 58G devices to production

* Revision change in one or more subcores


Video Processing Subsystem (2.2)

* Version 2.2

* General: Widened range for CSC to 0-255 when converting from YCbCr to RGB.

* General: Enabled 8PPC support

* General: Added compatibility for Vitis

* Revision change in one or more subcores


Video Scene Change Detection (1.0)

* Version 1.0 (Rev. 2)

* General: Added compatibility for Vitis


Video Test Pattern Generator (8.0)

* Version 8.0 (Rev. 2)

* General: Made changes for FID bit to toggle after every frame instead of every line.

* Revision change in one or more subcores


Video Timing Controller (6.2)

* Version 6.2

* Simplified VIDEO_MODE defaults to 3 standard resolutions.

* Updated the fine adjustment values for resolutions.


Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores


Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores


Video to SDI TX Bridge (2.0)

* Version 2.0

* No changes


Virtex UltraScale+ FPGAs GTM Transceivers Wizard (1.0)

* Version 1.0 (Rev. 4)

* General: Updated example design XDC to remove MAX_PROG_DELAY constraints

* General: Added a dynamic transcode bypass port for switching use cases

* General: Added system_management_wiz IP instance in example design for Temperature sensing

* Revision change in one or more subcores


Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3 (Rev. 6)

* General: Updated the device support


Viterbi Decoder (9.1)

* Version 9.1 (Rev. 12)

* General: polarity of CE changed in metadata. No change to functionality.

* Revision change in one or more subcores


XADC Wizard (3.3)

* Version 3.3 (Rev. 7)

* General: New Device support. No affect.


XHMC (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores


YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 13)

* No changes


ZYNQ UltraScale+ SYNC IP V1_0 (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


ZYNQ UltraScale+ VCU (1.2)

* Version 1.2 (Rev. 1)

* No changes


ZYNQ UltraScale+ VCU DDR4 Controller (1.1)

* Version 1.1

* Port Change: phy_Clk instead of UsrClk

* Port Change: phy_sRst instead of sRst_Out

* Bug Fix: NONE

* Feature Enhancement: Supports for BRAM and URAM

* Other: phy_Clk should be used instead of UsrClk

* Other: phy_sRst should be used instead of sRst_Out

* Revision change in one or more subcores


ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 6)

* No changes


ZYNQ7 Processing System VIP (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores


ZYNQMPSOC Processing System VIP (1.0)

* Version 1.0 (Rev. 6)

* Read response fixed

* Revision change in one or more subcores


Zynq UltraScale+ MPSoC (3.3)

* Version 3.3 (Rev. 1)

* Bug Fix: 1.Updated SPI Interface.

* Revision change in one or more subcores


Zynq UltraScale+ RF Data Converter (2.2)

* Version 2.2

* Bug Fix: Fixed demonstration testbench  ADC data checking for configurations where decimation rates are larger than 1

* Bug Fix: Extended calibration freeze process to freeze OCB1 calibration stage

* New Feature: Added support for PLL reference clock input divider

* Other: Moved the setting of the clock divider register to the initial configuration stage

* Other: Added registers in the example design data stimulus block to improve timing

* Other: Updated ADC interrupt register default values

* Other: Removed ADCx_Outdiv and DACx_Outdiv parameters as these should not be modified by the user

* Other: Reworked the generation of the ADC and DAC control buses

* Other: Example design no longer sets the default simulator to Questa


audio_tpg_v1_0 (1.0)

* Version 1.0

* No changes


axi_msg (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores


axi_sg (4.1)

* Version 4.1 (Rev. 13)

* Revision change in one or more subcores


gtm_cntrl (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores


interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes


lib_bmg (1.0)

* Version 1.0 (Rev. 13)

* Revision change in one or more subcores


lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes


lib_fifo (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores


lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes


lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes


 

AR# 72923
日付 03/05/2020
ステータス アクティブ
種類 一般
ツール