We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7323

FPGA Express 3.x: Global Clock Buffer is inserted, ignoring DONT USE in Express Constraints Editor


Keywords: Express, clock, buffer, BUFG, BUFGP, BUFGS, automatic, dont use,

Urgency: Standard

General Description:
FPGA Express will, by default, place global clock buffers on signals used as
clocks in your HDL code. There are times, when you do not wish to use a clock
buffer on that particular port, so FPGA Express allows you to override that
assignment via its Constraints Editor. This editor is available in the
Foundation Project Manager as well as in the standalone FPGA Express GUI.

Right-click on the pre-optimized design and select Edit Constraints (Edit
Synthesis Constraints... in Foundation). Under the Ports tab you will see a
column for Global Buffer. Normally, to tell FPGA Express to not use a global
buffer for a particular port you would select "DONT USE" in the row associated
with that input port. However, an issue in FPGA Express 3.x exists that may
ignore that setting.



If you see that a clock buffer is still inserted even though you have set that
port to DONT USE, use this workaround:

Change the Global Buffer setting in the first row, "<default>", from AUTOMATIC
to DONT USE. Then, assign global buffers to the ports that do require them by
changing the local value in the appropriate rows.

This problem is fixed in FPGA Express v3.4

AR# 7323
日付 08/27/2001
ステータス アーカイブ
タイプ 一般