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AR# 7331

Concept-HDL - GSR/GTS behavior does not simulate with RAMB4* Verilog models.

説明

Keywords: UNISIM, Verilog, Concept-HDL

Urgency: Standard

General Description:
The Concept-HDL behavioral models are not using the glbl.GSR methodology, but rather the GSR_SIGNAL methodology. This will lead to bad simulation results when toggling the GSR on a design with BlockRAM.

Please see (Xilinx Solution 6537) on the usage of the glbl module.
Please see (Xilinx Solution 3914) on the usage of the GSR_SIGNAL text macro.
Please see (Xilinx Solution 5009) for information on driving the GSR pin.

ソリューション

The UNISIM Verilog models for RAMB4* does not assign glbl.GSR and glbl.GTS to GSR and GTS, respectively. The behavioral models are using the GSR_SIGNAL methodology.

To resolve this issue, you can apply both methodologies for initializing GSR/GTS.

Please see (Xilinx Solution 6537) for information regarding the usage of the glbl module in the Xilinx Alliance 2.1 (or greater) software.

Please see (Xilinx Solution 3914) for information on the usage of the GSR_SIGNAL text macro.

Please see (Xilinx Solution 5009) for information on driving the GSR pin.
AR# 7331
作成日 08/31/2007
最終更新日 07/19/2001
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