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AR# 7340

2.1i TRCE - Paths are reported against the wrong timing constraint.

説明

2.1i TRCE shows several paths that are failing timing constraints. Investigation

shows that the failing paths are not being included in the correct timing constraints.

The failing paths show up in the period specification when they should show up in

another from GRP_CHIP to GRP_CHIP constraint (TS_Chip_rate1).

This problem is due to an overflow of an internal table, which consequently

causes identical paths from the period and exception timespec to appear different.

ソリューション

A fix for this problem is included in the 2.1i Service Pack 1 Update which is

scheduled to become available on September 1.

For more information about the 2.1i Service Pack 1 Update see:

(Xilinx Solution #7317)

AR# 7340
作成日 08/23/1999
最終更新日 01/18/2010
ステータス アーカイブ
タイプ 一般