AR# 7354

3.1i Timing Analyzer - Virtex-II - Advaned Analysis coverage is different than expected for SRLC16.

説明

keywords: advanced, analysis, SRLC16, coverage

概要:

During Advanced Analysis, the percent coverage is

different than expected for SRLC16.

ソリューション

The shift registers are being packed correctly into

both LUTs of the Slices.The real problem is that

the speed files are missing setup/hold times from

the Address to the Clock.Normally there is no

setup time for the Address lines, since they are

considered a data path.In this case, there

should be setup/hold times available.

This issue will be address in a future release.

AR# 7354
日付 01/18/2010
ステータス アーカイブ
種類 一般