General Description: FPGA Express 3.x writes out an NCF (Netlist Constraints File) for XC4000 and Spartan architectures as well as Virtex architectures. This file contains timing constraints and is read by NGDBUILD (Translate) along with all XNF (XC4000/Spartan) and EDIF (Virtex) netlist files.
An option exists within FPGA Express to maintain hierarchical boundaries within the design. This option is set by checking the Preserve Hierarchy box before synthesizing, or by setting individual levels to "Preserve" within the Express Constraints editor. A Virtex design will produce a single, hierarchical EDIF file, but an XC4000/Spartan design will produce multiple XNF files.
The NCF file has the same name as the top level netlist and is read by NGDBUILD immediately after that top level netlist. A problem will occur if the NCF file refers to instances found in lower level XNF files, which have not been read by NGDBUILD yet. An error like this one will occur:
ERROR:NgdHelpers:14 - Could not find INST(s) "sixty/lsbcount/QOUT_reg<0>" in design "watchver". INST entry is "INST "sixty/lsbcount/QOUT_reg<0>" TNM = "lowbits-To" ;
There are two possible solutions.
One is to flatten the design. This will produce a single XNF file that contains the entire design.
The other is to rename the <design>.NCF file to <design>.UCF. The UCF file is read after all the design netlists have been read in. Be sure that the <design>.NCF file no longer exists. In the Foundation Project Manager, this means running the Flow Engine in Interactive Mode, as launching it from the Implementation button will re-export the NCF file from synthesis.