Problem Description : When a core is generated using the Xilinx CORE Generator, the Verilog and VHDL instantiation template files (the .VEO and .VHO files, respectively) are written out in UNIX format. As a result, the text in these files appears to be merged into a single line if viewed in Windows Notepad because there are no carriage return characters in UNIX-formatted ASCII text files.
In addition, copying text out of WordPad and trying to paste it into the Foundation HDL Editor also results in all of the text being merged into a single line.
All report files written out by the Xilinx software are written out in UNIX format and should be readable using Windows WordPad
If you only have the Windows Notepad and WordPad tools available to you, but prefer to edit your files using Notepad, you can do the following to get around this problem:
1.Open the file in MS WordPad. (DO NOT cut the text out of Notepad and try to paste it into WordPad--it will not work.) 2.Save the file in "RICH TEXT FORMAT" 3.Now do a "Save As" "Text Document - MS-DOS format" (as opposed to a "plain" Text Document format).
This will replace the UNIX newlines with MS-DOS format newlines and allow you to subsequently edit the file using Notepad..
If you are using the Foundation HDL Editor in conjunction with the Xilinx Foundation toolset, open the instantiation template directly using the Foundation HDL Editor (in other words, don't open the file using WordPad). Any additional HDL files which need to be created using the template should also be created using the HDL Editor to ensure proper transfer of linefeeds and any other formatting information.