You can significantly speed up timing analysis and reduce memory requirements as follows:
In a design with multiple inputs clocked by a common clock that have the same setup requirements, and with individual OFFSET constraints created for each input, the timing analysis takes longer and requires more memory. Additionally, the timing report lists out each individual I/O as a constraint. If these requirements are handled with either global or groups of input OFFSET constraints, timing analysis is significantly faster and requires less memory. The timing report also lists one constraint followed by each of the input paths (this is true for outputs, as well.)
The Constraints Editor allows the creation of group OFFSET constraints from the Ports tab to help alleviate this problem. This will improve all timing-related run times (including timing-driven PAR).