UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7561

CPLD XPLA Professional - What does the attribute "ISTYPE INVERT" do?

説明

Keywords: XPLA Professional, CoolRunner, fitter, attribute, ISTYPE,
INVERT, PHDL, ABEL

Urgency: Standard

General Description:
What does the attribute "ISTYPE INVERT" do?

ソリューション

This attribute only has meaning for registered signals; it has no meaning for combinatorial
equations. The software will remove this attribute for combinatorial equations at the first
stage of normalization before any further processing.

ISTYPE INVERT means that there is an inverter between the macrocell register and
the output buffer. If the user specifies ISTYPE INVERT for 22v10 devices, the software
keeps the inverter. However, since XPLA devices do not have an inverter between the
macrocell register and the output buffer, this will be emulated.

For example (please note the spacing):

Source code:

O1 pin istype 'reg, invert';
O2, O3 pin istype 'com';
AR, CLK, IN pin;

O1.d = IN;
O1.AR = AR;
O1.CLK = CLK;
O2 = O1.Q;
O3 = O1.FB;


Resulting Equations for XPLA Devices:

!O1.d = IN; " Inversion occurs at the D input
O1.AP = AR; " note that AP is now used
O1.CLK = CLK;

O2 = !O1.q; " Inversion of the Q output occurs to negate the inversion
"at the D input
O3 = !O1.q;

Resulting Equations for 22V10 Devices:

O1.d = IN;
O1.AR = AR;
O1.CLK = CLK;

O2 = O1.q;
O3 = O1.q;
AR# 7561
作成日 09/15/1999
最終更新日 04/20/2001
ステータス アーカイブ
タイプ 一般