We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7650

XPLA1: Internally created asynchronous global clocks disable pins for use as inputs.


Keywords: XPLA, CoolRunner, XPLA1, asynchronous, global, clocks,
internal, disable, pin, input

Urgency: Standard

General Description: Why do the internally created asynchronous
global clocks in XPLA1 devices disable pins for use as inputs?


If a global clock is created internally by an equation, the associated pin
will be disabled for use as an external input. In other words, the clock
signal will not be treated as a node which would have permitted an
external signal to drive the device on the pin associated with that

The internal clock circuitry samples the signal between the macrocell
output buffer and the pin. The architecture is set up this way to allow an
external clock to drive the pin while an internal signal can use the
macrocell as a node. This prevents wasted resources.
AR# 7650
日付 10/03/2008
ステータス アーカイブ
種類 一般