UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7672

CPLD XPLA2 - How many I/O pins are available per fast module?

説明

Keywords: XPLA, CoolRunner, XPLA2, I/O, pins, fast, module

Urgency: Standard

General Description:
How many I/O pins are available in an XPLA2 fast module?

ソリューション

There are 32 I/O pins connected to each fast module, and they are organized
8 per logic block.
AR# 7672
作成日 08/31/2007
最終更新日 10/03/2008
ステータス アーカイブ
タイプ 一般