We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7775

2.1i Foundation - LOCKED signal does not go high on CLKDLL during Timing Simulation


Keywords: dll, lock, simulation, high, Virtex, fndtn

Urgency: Standard

General Description: During Timing Simulation of the CLKDLL, the LOCKED output signal never goes high. This limitation is the result of simulation resolution in the Foundation Logical Simulator . Currently the resolution is limited to 100ps. In order for the CLKDLL to lock the resolution must be set to 1ps.


There are two workarounds:

1- Manually apply stimulus to the CLKDLL LOCKED signal to
drive it high at 300ns. This will allow more than enough time
to model the LOCKED signal on the board.

2- Use a third party simulator such as Modelsim where the
resolution can be set to 1ps.
AR# 7775
日付 03/12/2002
ステータス アーカイブ
タイプ 一般