We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7784

2.1i COREGEN USER GUIDE: Errata sheet


Keywords: coregen, user, guide, errata

Urgency: standard

General Description:

Errata listing for the 2.1i CORE Generator User Guide


V2.1i CORE Generator User Guide Errata

(Xilinx Solution #6693) - V2.1i COREGEN USER GUIDE: Permissions for $XILINX/coregen/ip
directory do not need to be 777

Design Flows
Verilog behavioral simulation flow

(Xilinx Solution #6831) - V2.1i COREGEN USER GUIDE, VERILOG: "Error! Module name
previously declared" / Verilog parent design example contains redundant module declaration

(Xilinx Solution #6596) - V2.1i COREGEN, MTI, VERILOG: "WARNING[xx]:
.../XilinxCoreLib/xxxx.v(xx): Redefinition of macro: true" (or TRUE, false, or FALSE) when
analyzing/compiling COREGEN Verilog behavioral models

VHDL behavioral simulation flow

(Xilinx Solution #6861) - V2.1i COREGEN USER GUIDE, MTI, VHDL flow: 'Error
xxxmyadder8.vhd(20): near "myadder8_top" expecting COMPONENT' in VHDL
testbench example
AR# 7784
日付 08/01/2001
ステータス アーカイブ
種類 一般