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AR# 7819

FPGA Configuration - In master mode, how many CCLKs are given after DONE goes high in a 4000X part?


General Description: How many CCLKs will a 4kX part in master

mode give after DONE goes high?


The 4kX part will give one more rising edge if the Sync-To-Done capability is

selected in the Bitgen options. If Sync-To-Done is not selected, the

number of CCLKs given after DONE goes high is determined by the

number of Startup Cycles left after DONE goes high. The Defaults are:


OutputsActive: C3

GSRInactive: C4

Three rising edges (C2, C3, and C4) will be given after DONE goes high.

Even if other cycles are chosen for OutputsActive and GSRInactive,

the number of cycles given will take the sequence through C4.

If DONE is selected to go high on C4, there will be no further rising

edges after DONE goes high.

AR# 7819
日付 12/15/2012
ステータス アクティブ
タイプ 一般