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AR# 7820

FPGA Configuration: What is the maximum time PROG can be held low to delay configuration?

説明

Problem description: I would like to delay the configuration of my FPGA for some time after power-up. 

Are there any limitations as to how long I can delay configuration for?

ソリューション

(Xilinx Solution 492) states that the minimum pulse on the PROG pin must be 300ns. 

 

However, there is also a practical maximum time for which the PROG pin should be held low. 

 

It is not advisable to hold PROG low for more than 500 microseconds. 

To delay configuration for an arbitrarily long time, hold /INIT low instead. 

 

NOTE: This information was extracted from (Xilinx XAPP122). 

 

IMPORTANT: This does NOT hold for VIRTEX devices: there is NO maximum (XAPP138).

AR# 7820
作成日 08/21/2007
最終更新日 03/04/2014
ステータス アーカイブ
タイプ 一般