We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 7856

Viewlogic VHDL simulation:How to simulate Xilinx Virtex primitives (e.g. ramb4_s4)


Keywords: viewlogic, fusion, primitive, ram
Urgency: Normal
Problem Description:
When customer is simulating in Viewlogic, the Xilinx primitives such as ramb4_s4 will not simulate.


For functional simulation, you want to use the UNISIM and not the SIMPRIM
library. Under vhdl\src\unisims, you want to compile the following files in order:


This will allow to simulate instantiated components in your code like a

For timing simulation, Xilinx distributes a VHDL library for the RAMB4_S4_S4 that you have to compile in SpeedWave before you compile the model containing the instance of the primitive. When you get into Fusion, open the Library Manager and create a library SIMPRIM. From your Xilinx install directory (xilinx), add the file xilinx\vhdl\src\simprims\simprim_Vpackage.vhd and analyze. Then, in your user library, add xilinx\vhdl\src\simprims\simprim_VITAL.vhd and analyze. Then add and analyze your file that instantiates the RAMB4_S4_S4, e.g.
AR# 7856
日付 11/13/2002
ステータス アーカイブ
種類 ??????