entity spblkrams is port(CLK : in std_logic; EN : in std_logic; RST : in std_logic; WE : in std_logic; ADDR : in std_logic_vector(11 downto 0); DI : in std_logic_vector(15 downto 0); DORAMB4_S4 : out std_logic_vector(3 downto 0); DORAMB4_S8 : out std_logic_vector(7 downto 0)); end;
architecture struct of spblkrams is
component RAMB4_S4 port (DI : in STD_LOGIC_VECTOR (3 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; RST : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (9 downto 0); DO : out STD_LOGIC_VECTOR (3 downto 0)); end component;
component RAMB4_S8 port (DI : in STD_LOGIC_VECTOR (7 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; RST : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (8 downto 0); DO : out STD_LOGIC_VECTOR (7 downto 0)); end component;
attribute INIT_00: string; attribute INIT_00 of INST_RAMB4_S4: label is X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"; attribute INIT_00 of INST_RAMB4_S8: label is X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100";
begin
INST_RAMB4_S4 : RAMB4_S4 port map ( DI => DI(3 downto 0), EN => EN, WE => WE, RST => RST, CLK => CLK, ADDR => ADDR(9 downto 0), DO => DORAMB4_S4 );
INST_RAMB4_S8 : RAMB4_S8 port map ( DI => DI(7 downto 0), EN => EN, WE => WE, RST => RST, CLK => CLK, ADDR => ADDR(8 downto 0), DO => DORAMB4_S8 );