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AR# 7948

2.1i 9500/xl Tsim- Timing model incorrect for negative edge triggered global clock signals

説明

Keywords: 9500, timing, negative, global clock

Urgency: Standard

General Description:
There is an error in the timing model such that the timing for
a negative edge triggered flip flop on the global clock net
uses the timing for a product-term clock net - thus appearing
slower than it really operates. This problem is not seen for
positive edge triggered registers.

ソリューション

This is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
AR# 7948
作成日 10/27/1999
最終更新日 08/27/2001
ステータス アーカイブ
タイプ 一般