General Description: FPGA Express 3.3 may report the following error:
Error: Buffer allocation detected possible drivers on the same net as clock input '/virtex_clk-Optimized/clk'. (FPGA-buffermap-25)
This error may occur when a clock signal sources inferred flip flops and other non-clock loads (combinatorial logic and/or black boxes). This been seen when FPGA Express infers a clock buffer on this signal or when the user specifies a clock buffer via the Express Constraints editor.
In any case, the workaround is to instantiate the clock buffer in your HDL code.