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What is the input clock frequency range for Virtex-E CLKDLLs to be locked?
For -6 parts:
Min(Mhz) Max(Mhz)
CLKDLL: 25 130
CLKDLLHF: 60 260
For -7 parts:
Min(Mhz) Max(Mhz)
CLKDLL: 25 160
CLKDLLHF: 60 320
AR# 8006 | |
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日付 | 05/14/2014 |
ステータス | アーカイブ |
種類 | 一般 |