UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8006

Virtex-E CLKDLL - What is the input clock frequency range for Virtex-E CLKDLLs to be locked?

説明

What is the input clock frequency range for Virtex-E CLKDLLs to be locked?

ソリューション

For -6 parts: 

 

Min(Mhz) Max(Mhz) 

CLKDLL: 25 130 

CLKDLLHF: 60 260 

 

For -7 parts: 

 

Min(Mhz) Max(Mhz) 

CLKDLL: 25 160 

CLKDLLHF: 60 320

AR# 8006
作成日 08/21/2007
最終更新日 05/14/2014
ステータス アーカイブ
タイプ 一般