AR# 8033: 2.1i COREGEN, C_IP3, Binary Counter: clock latency prior to the start of counting is not modeled in the behavioral models
2.1i COREGEN, C_IP3, Binary Counter: clock latency prior to the start of counting is not modeled in the behavioral models
Keywords: Coregen, binary, counter, latency
General Description: The Binary Counter shows a clock latency of 100 ns before it initially starts counting in functional (post ngdbuild) and timing simulations, but this latency does not appear to be modeled in the counter's behavioral models.
The Binary Counter simulation model does not model the latency associated with the reset that occurs during power-up. If you need to model this latency, you can use the Reset on Configuration (ROC) primitive. This primitive is automatically inserted into the VHDL simulation netlist by NGD2VHDL when you create timing (and post-NGDBuild) VHDL simulation netlists if you do not have a Startup block in the design.
You can avoid the default 100ns delay associated with power-on reset in the post-NGDBuild and timing simulation netlists by selecting the following option:
Implementation (or Design) -> Options -> Edit Options (Simulation) -> VHDL/Verilog tab -> Bring Out Global Set/Rest Net as Port.