Description:
How do I LOC logic to specific CLBs using Synplify and either VHDL or Verilog?
Using VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity flops is port(
di: in std_logic;
ce : in std_logic;
clk: in std_logic;
qo: out std_logic;
rst: in std_logic);
end flops;
architecture inst of flops is
component FDCE port( D: in std_logic;
CE: in std_logic;
C: in std_logic;
CLR: in std_logic;
Q: out std_logic);
end component;
attribute LOC: string;
attribute LOC of U0: label is "CLB_R2C3.S0";
attribute LOC of U1: label is "CLB_R2C4.S0";
attribute LOC of U2: label is "CLB_R6C8.S0";
signal q0,q1 : std_logic;
begin
U0 : FDCE port map(D => di,
CE=> ce,
C => clk,
CLR => rst,
Q => q0);
U1: FDCE port map(D => q0,
CE=> ce,
C => clk,
CLR => rst,
Q => q1);
U2: FDCE port map(D => q1,
CE=> ce,
C => clk,
CLR => rst,
Q => qo);
end inst;
Using Verilog
module flops (di, ce, clk, qo, rst);
input di;
input ce;
input clk;
output qo;
input rst;
wire q0, q1;
FDCE u0(.D(di),
.CE(ce),
.C (clk),
.CLR (rst),
.Q (q0))/*synthesis loc="CLB_r2c3.s0" */;
FDCE u1 (.D (q0),
.CE(ce),
.C (clk),
.CLR(rst),
.Q (q1))/* synthesis loc="CLB_r4c5.s1" */;
FDCE u2(.D (q1),
.CE(ce),
.C (clk),
.CLR (rst),
.Q (qo)) /* synthesis loc="CLB_r6c2.s0" */;
endmodule
AR# 8056 | |
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日付 | 05/14/2014 |
ステータス | アーカイブ |
種類 | 一般 |