General Description: The following problems may be seen with the Verilog model for the 4K Constant Coefficient Multiplier core when simulating in Synopsys VCS or Verilog-XL:
1. There is no latency between the input transitions and output transitions--the output changes immediately after a new input value is clocked in. 2. Race condition associated with transitioning of the output on a rising clock edge
The problems are similar to those found in the Virtex Dynamic Constant Coefficient Multiplier Verilog model as described in (Xilinx Solution #8020). The symptoms show up in VCS and Verilog-XL.
An alternative workaround is to generate a post-NGDBUILD simulation netlist for the core in place of its behavioral model. Please refer to (Xilinx Solution #8065) for details on how to do this.