CLKDLL BCLK_dll_OUT // off-chip synchronization (.CLKIN(ACLK_ibufg), .CLKFB(BCLK_ibufg), // BCLK and OUTBCLK is connected outside the chip. .RST(1'b0), .CLK2X(OUTBCLK), //connected to BCLK outside .CLK0(), .CLK90(), .CLK180(), .CLK270(), .CLKDV(), .LOCKED(BCLK_LOCK) );
always @(posedge ACLK_2x_design or posedge RESET) begin if (RESET) QOUT[1:0] <= 2'b00; else if (ACLK_lock) QOUT[1:0] <= DIN[1:0]; end
endmodule
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VHDL の例 library IEEE; use IEEE.std_logic_1164.all;
library unisim; use unisim.vcomponents.all;
entity CLOCK_TEST is port( ACLK : in std_logic;
-- off chip feedback, connected to OUTBCLK on the board. BCLK : in std_logic;
--OUT CLOCK OUTBCLK : out std_logic;
DIN : in std_logic_vector(1 downto 0); RESET : in std_logic; QOUT : out std_logic_vector (1 downto 0);
-- CLKDLL lock signal BCLK_LOCK : out std_logic ); end CLOCK_TEST;
architecture RTL of CLOCK_TEST is
component IBUFG port ( I : in std_logic; O : out std_logic); end component;
component BUFG port ( I : in std_logic; O : out std_logic); end component;
component CLKDLL port ( CLKIN : in std_logic; CLKFB : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; LOCKED : out std_logic); end component;
-- Glock signals signal ACLK_ibufg : std_logic; signal BCLK_ibufg : std_logic; signal ACLK_2x : std_logic; signal ACLK_2x_design : std_logic; signal ACLK_lock : std_logic;
begin
ACLK_ibufg : IBUFG port map ( I => ACLK, O => ACLK_ibufg );
BCLK_ibufg : IBUFG port map ( I => BCLK, O => BCLK_ibufg );
ACLK_bufg : BUFG port map ( I => ACLK_2x, O => ACLK_2x_design );
process (ACLK_2x_design, RESET) begin if RESET = '1' then QOUT <= "00"; elsif ACLK_2x_design'event and ACLK_2x_design = '1' then if ACLK_lock = '1' then QOUT <= DIN; end if; end if; end process;