library ieee; use ieee.std_logic_1164.all; library virtex; use virtex.components.all;
entity lut_ex is port ( LUT1_IN, LUT2_IN : in std_logic_vector(1 downto 0); LUT1_OUT, LUT2_OUT : out std_logic_vector(1 downto 0)); end entity lut_ex;
architecture XILINX of LUT_EX is
component LUT1 port (O : out std_logic; I0 : in std_logic); end component;
component LUT2 port (O : out std_logic; I0, I1 : in std_logic); end component;
begin
-- LUT1 used as an inverter U0 : LUT1 port map (O => LUT1_OUT(0), I0 => LUT1_IN(0)); -- LUT1 used as a buffer U1 : LUT1 port map (O => LUT1_OUT(1), I0 => LUT1_IN(1));
-- LUT2 used as a 2-input AND gate U2 : LUT2 port map (O => LUT2_OUT(0), I1 => LUT2_IN(1), I0 => LUT2_IN(0)); -- LUT2 used as a 2-input NAND gate U3 : LUT2 port map (O => LUT2_OUT(1), I1 => LUT2_IN(1), I0 => LUT2_IN(0));