In order for the 3000, 4000, or 5200 series FPGA to enter the Startup Sequence and complete the configuration process, two conditions must be met:
- All Data Frames must be correctly loaded into memory resulting in the memory being Full.
- LengthCount Match must occur.
LengthCount Match occurs when the total number of CCLK cycles used so far in the configuration process is equal in value to the 24-bit LengthCount number in the header of the bitstream.
LengthCount Match must occur after all Data Frames have been loaded and the configuration memory is full. If LengthCount Match happens too early (before memory is full), then the 24-bit LengthCount counter will need to "roll over" before these conditions can both be satisfied. This can be tested by applying (or allowing the FPGA to apply) 2^24 (~18,000,000) extra CCLK cycles.
This condition can be caused by applying (or allowing the FPGA to apply) extra CCLK cycles at the beginning of the configuration process prior to loading the Preamble. This can be verified by checking again how many fill bits are observed on DOUT prior to the Preamble. The number should not be more than 8 plus 1.5 CCLK delay time.
Another possible cause might be that the configuration process was not allowed to complete or was terminated too early. Check that the CCLK is still running (Master only). Even after LengthCount Match has been satisfied, additional clocks are required to enter and complete the Startup Sequence. (NOTE: The total number of bits in a configuration stream are always greater than the LengthCount Number.)