AR# 8335

XST - XST evaluates "?" in case statements as a "don't care" ("-")

説明

In the Verilog Language, "?" is defined as representing a "don't care" ("-"). However, most synthesis tools do not support the use of a "?" and evaluate it as false. 

 

XST fully supports the use of "?" and properly evaluates expressions using this construct. The following code example creates a MUX based on the select bit being used. (Other synthesis tools simply assign out to Ground.) 

 

case (select) 

3'b1?? : out = 2'b01; 

3'b?1? : out = 2'b11; 

3'b??1 : out = 2'b10; 

default : out = 2'b00; 

endcase

ソリューション

This difference will result in simulation, synthesis, and implementation results that differ from those of other synthesis vendors.  

 

NOTE: XST is correctly synthesizing the use of this construct.

AR# 8335
日付 05/14/2014
ステータス アーカイブ
種類 一般