We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 834

Hardware Debugger 6.0.1: Nets split during implementation are shown as split nets in available signals list


Split nets are nets that are created when the implementation software needs
to route a particular net from one source to multiple loads and uses CLBs to
split the original net creating several "source" connections. When split
nets are created, all the nets will appear in the available signals list


When split nets are displayed in the available signals list box, any one of
the nets can be chosen to be displayed in a waveform or used to create a
group. Typically, the smallest split net should be chosen. When the design
is re-implemented, the split nets chosen may need to be re-added to the
display list or to any groups which reference them.
AR# 834
日付 11/10/2004
ステータス アーカイブ
種類 一般