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AR# 8413

CORE Generator - Can I combine smaller Xilinx Asynchronous FIFO cores together in parallel, or cascade them in a series?


Can I combine smaller Xilinx Asynchronous FIFO Cores together in parallel, or cascade them together in a series to create larger or deeper FIFOs?


Xilinx strongly recommends that you do not try to combine multiple Asynchronous FIFO cores together to create wider or deeper FIFOs.  


Suppose you try to combine the FIFO cores in parallel to achieve a wider data width, iIf your Read and Write clocks are asynchronous, it is likely that the two halves of the combined FIFO will get out of sync at some point. This would cause the Read data to be corrupted (each half would be from a different data word). The only way to recover from such a condition would be to reset, which would result in a loss of all stored data.  


A parallel arrangement might be possible if your Read and Write clocks are synchronous (that is, driven by the same clock source). It might also be possible if you could guarantee that you would never perform overlapping Write and Read operations (i.e., at any point in time a Write or Read might be performed, but never both). Under these conditions, the chances of the two FIFOs becoming out of sync will be greatly reduced, although it cannot be guaranteed that they will stay in sync.  


Trying to cascade the Asynchronous FIFOs in series to increase their depth is an even more complex proposition, as you would have to create additional control logic to generate status flags and to gate Read and Write operations between the two FIFOs. You would also have to multiplex the data outputs. As this task is so complex, it would be easier to build the FIFO for your particular requirements from the ground up. For information on this, Please see (Xilinx XAPP131); "170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature" v1.6.

AR# 8413
日付 05/14/2014
ステータス アーカイブ
タイプ 一般