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AR# 8733

3.1i COREGEN: Verilog and VHDL simulation flows

説明

Keywords: 3.1i, verilog, vhdl, simulation

Urgency: standard

General Description:

This solution describes the Verilog and VHDL behavioral simulation flows for the 3.1i release.
The flows are similar to the 2.1i flows, with a number of enhancements added:

ソリューション

1

Verilog Simulation Flow
-------------------------------------

For details on the MTI flow, please refer to (Xilinx Answer # )
For details on the VCS flow, please refer to (Xilinx Answer #)
For details on the Verilog-XL flow, please refer to (Xilinx Answer #)
For details on the NC-Verilog flow, please refer to (Xilinx Answer #)

2

VHDL Simulation flow
----------------------------------

For details on the MTI flow, please refer to (Xilinx Answer # )
For details on the VSS flow, please refer to (Xilinx Answer #)
AR# 8733
作成日 03/02/2000
最終更新日 08/23/2002
ステータス アーカイブ
タイプ 一般