UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8778

3.1i COREGen, Leapfrog - CORE Generator VHDL models use non-IEEE standard std_logic_unsigned & std_logic_arith libraries

説明

Keywords: 1164, summit, leapfrog, vhdl, NC VHDL,

Urgency: Standard

General Description:
The CORE Generator VHDL models use non-IEEE standard std_logic_arith
package and std_logic_unsigned libraries. These packages are not part of
the IEEE 1164 standard. They are actually a Synopsys library that is supported
by MTI, but not by Cadence Leapfrog.

This prevents users of the Cadence Leapfrog and Summit simulators from
performing behavioral simulation of COREGen modules, since these simulators
comply with the IEEE 1164 standard and do not ship these libraries. There may
also be other simulators by Cadence which may not support these libraries, either.

ソリューション

1

There is no workaround for this issue at this time other than
going into post-NGDBuild, post-MAP or post-PAR simulation.

See (Xilinx Answer #8065) on how to generate these simulation files.

2

No future Core Generator behavioral models will contain
std_logic_arith and std_logic_unsigned.

The new models will be released in the update scheduled for
November 2000.
AR# 8778
作成日 03/08/2000
最終更新日 08/23/2002
ステータス アーカイブ
タイプ 一般