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AR# 8830

FPGA Express - Is there a way to globally disable the Shift Register LUT (SRL) Optimization?

説明

Keywords: shift, register, LUT, SRL, optimization, disable

Urgency: Standard

General Description:
I am synthesizing an FPGA Express project, and I would like to prevent my pipeline
registers from being combined into a shift register LUT. Does FPGA Express have a
setting to disable this?

ソリューション

1

To work around this, write Verilog or VHDL components such that a register gets
inferred:

VHDL

process(clk) begin
if clk'event and clk = '1' then
q<=d;
end if;
end process;

Verilog

always @ (posedge clk) q = d;


Instantiate this component as many times as needed. Make sure the "retain hierarchy"
is selected when synthesizing. (You will get flip-flops instead of the SRL16's.)

2

The SRL16 component does not have any sets/resets. Creating a delay element
with a synchronous or asynchronous set/reset will force FPGA Express to use flip-flops.

To implement a synchronous set/reset in FPGA Express, a special attribute has to be
passed. For more information, please see (Xilinx Solution 3992).

AR# 8830
作成日 03/16/2000
最終更新日 08/11/2003
ステータス アーカイブ
タイプ 一般