dout = data & latch # dout & !latch # dout & data; // redundant product term
// dout_temp = data & latch # data & dout; // dout = dout_temp # data & !latch; // redundant pterm END
There are two forms of a combinational latch given; the commented lines are necessary for the alternate form. The commented version may be useful for situations where the data equation is large. Because of the "retain" attribute, when the data equation is large, the software will not be able to appropriately minimize the logic, which results in high Product Term usage.
2
<b>VHDL</b> を使用して、レジスタ付きのラッチを作成する方法を次に示します。
library IEEE; use IEEE.std_logic_1164.all;
entity top is port ( gate: in STD_LOGIC; din: in STD_LOGIC; dout: out STD_LOGIC ); end top;
architecture top_arch of top is begin
process (GATE, DIN) begin if GATE='1' then DOUT <= DIN; end if; end process;
end top_arch;
3
<b>Verilog</b> を使用して、レジスタ付きのラッチを作成する方法を次に示します。
module top (DIN, GATE, DOUT) ;
input DIN ; input GATE ; output DOUT ; reg DOUT ;
always @ (GATE or DIN) begin if(GATE) DOUT =DIN; end