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AR# 8865

2.1i COREGEN - C_COUNTER_BINARY_V1_0.v Verilog behavioral model does not respond correctly to clock enable when Count To value is reached


Keywords : COREGEN, counter, behavioral, model, clock, enable, verilog,
virtex, terminal, count, value

Urgency : Standard

General Description : When performing a Verilog behavioral simulation of the
CORE Generator Binary Counter, the counter does not stop at the terminal value
when the clock enable is de-asserted--it resets to zero before it stops counting.


The problem is that the behavioral model code does not take the clock enable into
account when the terminal count is reached, so the count resets To correct this
behavior, the clock enable signal, intCE, must be used to qualify the intSCLR_RESET
assignment that is made on line 222 of the C_COUNTER_BINARY_V1_0.v
model. Currently it reads:

wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && C_RESTRICT_COUNT
== 1)) && ~intLOAD;

This should be replaced with the following:

wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE &&
C_RESTRICT_COUNT == 1)) && ~intLOAD;
AR# 8865
日付 09/05/2001
ステータス アーカイブ
種類 一般