UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8888

MTI, VHDL, COREGEN, C_IP4: "# WARNING[10]: ./XilinxCoreLib/vfft64.vhd(7177): Duplicate signals in sensitivity list."

説明

Keywords: start, modelsim, vhdl, compilation

The following warning may be seen when compiling the XilinxCoreLib VHDL library
from the C_IP4 IP update:

"# WARNING[10]: ./XilinxCoreLib/vfft64.vhd(7177): Duplicate signals in sensitivity list."

The problem is that the vhdl model, vfft64.vhd, in the XilinxCorelib directory has a
duplicate "start" signal in the sensitivity list for the process, "wren_proc". In C_IP4,
this occurs on line 1660 of the model.

The errant line looks like this:

wren_proc : process(clk,ce,rs,start,mwr,start,busy_i,mode)
^ ^

Note the presence of two signals named "start" in the sensitivity ist.

ソリューション

Edit the vfft64.vhd model in your XilinxCoreLib library directory, delete the
second "start" signal in the sensitivity list of the wren_proc process, save
your changes, and then recompile the XilinxCoreLib library.
AR# 8888
作成日 08/21/2007
最終更新日 09/10/2008
ステータス アーカイブ
タイプ 一般