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The following warning may be seen when compiling the XilinxCoreLib VHDL library from the C_IP4 IP update:
"# WARNING: ./XilinxCoreLib/vfft64.vhd(7177): Duplicate signals in sensitivity list."
The problem is that the vhdl model, vfft64.vhd, in the XilinxCorelib directory has a duplicate "start" signal in the sensitivity list for the process, "wren_proc". In C_IP4, this occurs on line 1660 of the model.
Note the presence of two signals named "start" in the sensitivity ist.
Edit the vfft64.vhd model in your XilinxCoreLib library directory, delete the second "start" signal in the sensitivity list of the wren_proc process, save your changes, and then recompile the XilinxCoreLib library.