2. サポート
  3. AR# 8904: 3.1i XST - How do I add the IOB=TRUE attribute to output flip flops in XST?

AR# 8904

3.1i XST - How do I add the IOB=TRUE attribute to output flip flops in XST?

説明


General Description:

Currently, the IOB=TRUE attribute must be applied to the internal signals driven by flip-flops in order to be processed. (If the attribute is placed on the port signal, it gets applied to the I/O buffer). This methodology works for input FFs, output 3-state FFs, and output FFs that will be placed in a 3-state condition, but not for direct output FFs.



NOTE: With the 4.1i software release, the IOB attribute can be placed directly onto the port.

ソリューション


In the case of an output flip-flop, a work-around is to assign the "IOB=TRUE" attribute to an intermediate signal that connects to the output of the flip-flop and to the output port.



VHDL Example:



library IEEE;

use IEEE.std_logic_1164.all;



entity OUT_FLIP_FLOP is

port (DIN : in std_logic;

CLK, RST : in std_logic;

DOUT : out std_logic);

attribute IOB : string;



end OUT_FLIP_FLOP;



architecture OUTFF_arch of OUT_FLIP_FLOP is



signal DOUT_INT : std_logic;

attribute IOB of DOUT_INT : signal is "TRUE";



begin



clocked : process(CLK, RST)

begin



if (RST = '1') then

DOUT_INT <= '0';

elsif rising_edge(CLK) then

DOUT_INT <= DIN;

end if;



end process;



DOUT <= DOUT_INT;



end OUTFF_arch;



Verilog Example:



module iobflops (dout, clk, rst, din);

output dout;



input clk, rst, din;

reg dout,dout_int;



//synthesis attribute IOB of dout_int is "TRUE"



always@(posedge clk or posedge rst)



begin

if (rst) dout_int = 1'b0;

else dout_int = din;

end



always@(dout_int) dout=dout_int;



endmodule
AR# 8904
日付 09/09/2010
ステータス アーカイブ
種類 一般