General Description:
When I compile a VHDL program using Synplicity's Synplify 5.3.0, the following error is reported:
"Process must contain at least one wait."
What does this error mean, and how do I avoid it?
This error occurs when a user compiles a VHDL design using a process statement that does not include any incoming signals in the sensitivity list of the process.
For example, the following code would cause the error:
process
if ( CLK = '1' and CLK'event ) then
DATA_OUT <= DATA_IN;
end if;
end process;
The correct way to specify a process is to include all the signals in the sensitivity list, as shown below:
process ( CLK, DATA_IN )
if ( CLK = '1' and CLK'event ) then
DATA_OUT <= DATA_IN;
end if;
end process;
AR# 8940 | |
---|---|
日付 | 05/14/2014 |
ステータス | アーカイブ |
種類 | 一般 |