-------------------------------------------------------------------------------- -- Reed-Solomon Decoder Wrapper Example -- Copyright 1999 Xilinx, Inc. All rights reserved. --------------------------------------------------------------------------------
ENTITY rsdec_wrap IS PORT ( data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); sync : IN STD_LOGIC; reset : IN STD_LOGIC; clk : IN STD_LOGIC; ce : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); blk_strt : OUT STD_LOGIC; blk_end : OUT STD_LOGIC; err_found : OUT STD_LOGIC; err_cnt : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); fail : OUT STD_LOGIC; ready : OUT STD_LOGIC); END rsdec_wrap;
ARCHITECTURE example OF rsdec_wrap IS
COMPONENT xil_rsdecoder PORT ( data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); sync : IN STD_LOGIC; reset : IN STD_LOGIC; clk : IN STD_LOGIC; ce : IN STD_LOGIC := '1'; data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); blk_strt : OUT STD_LOGIC; blk_end : OUT STD_LOGIC; err_found : OUT STD_LOGIC; err_cnt : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); fail : OUT STD_LOGIC; ready : OUT STD_LOGIC ); END COMPONENT;
COMPONENT STARTUP PORT (GSR : IN STD_LOGIC); END COMPONENT;
COMPONENT BUFG PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC); END COMPONENT;