We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8981

EXEMPLAR - How do I read a CORE Generator file for timing analysis?


Keywords: coregen, spectrum, leonardo, core generator, timing

Urgency: Standard

General Description:
Exemplar Leonardo Spectrum 1999.1j and later can perform device utilization and
timing analysis for CORE Generator macros in the design. Leonardo Spectrum will
read the CORE Generator EDIF netlist and include the macro's size and timing
information in the design report.


Use the following command to read the EDIF netlist:

read_coregen <edif_file>

Here is an example tcl file:

# load the library
load_lib xcv
set part v50ecs144
# source coregen tcl script
source read_coregen.tcl

#read the coregen netlist
read_coregen coremodule.edn

#read the top level
read top.vhd

optimize -ta xcv

#area report
report_area -c

# timing analysis
report_delay -longest

auto_write spectrum.edf
AR# 8981
日付 11/24/2003
ステータス アーカイブ
種類 一般