AR# 9017: 2.1i XC9500 Family Hitop - Hi805 - Multiple sites/pin locks for a single signal not allowed.
AR# 9017
2.1i XC9500 Family Hitop - Hi805 - Multiple sites/pin locks for a single signal not allowed.
説明
Keywords: hitop, pin, lock, multiple
Urgency: Standard
General Description: For Xilinx FPGAs, you may give the placer multiple sites to lock a single signal to. Example: NET dout_reg LOC=P1,P2;
When I try this syntax for the XC9500 family, I get: hi805 - DOUT_REG is assigned to an invalid location (P1,P2) for this device. This will prevent this design from fitting on the current device.
ソリューション
This feature was added to Xilinx software as of 4.1i.