library IEEE, virtex,synplify; use IEEE.std_logic_1164.all; use virtex.components.all; use synplify.attributes.all; entity setreset is port (CLK: in std_logic; DIN1, DIN2, DIN3: in STD_LOGIC; SET, RESET: in STD_LOGIC; DOUT1, DOUT2, DOUT3: out STD_LOGIC); attribute xc_loc of CLK: signal is "A11"; end setreset ;
architecture RTL of setreset is component BUFG port (i: in std_logic; o: out std_logic); end component;
signal CLKIN: std_logic; begin bufginst: BUFG port map(i => CLK, o => CLKIN);
set_then_reset: process (CLKIN, SET, RESET) begin if (SET = '1') then DOUT1 <= '1'; elsif (RESET = '1') then DOUT1 <= '0'; elsif ( CLKIN'event and CLKIN ='1') then DOUT1 <= DIN1; end if; end process;
reset_then_set: process (CLKIN, SET, RESET) begin if (RESET = '1') then DOUT2 <= '0'; elsif (SET = '1') then DOUT2 <= '1'; elsif ( CLKIN'event and CLKIN ='1') then DOUT2 <= DIN2; end if; end process;
set_only: process (CLKIN, SET) begin if (SET = '1') then DOUT3 <= '1'; elsif (CLKIN'event and CLKIN = '1') then DOUT3 <= DIN3; end if; end process; end RTL;
2
// Verilog example // Note: $SYNPLICITY is the Synplicity install directory.
BUFG bufginst(.I(CLK), .O(CLKin)); always @ (posedge SET or posedge RESET or posedge CLKin) begin: set_then_reset if (SET) DOUT1 <= 1'b1; else if (RESET) DOUT1 <= 1'b0; else DOUT1 <= DIN1; end
always @ (posedge RESET or posedge SET or posedge CLKin) begin: reset_then_set if (RESET) DOUT2 <= 1'b0; else if (SET) DOUT2 <= 1'b1; else DOUT2 <= DIN2; end