entity clockdll_design is port (clk_in : in std_logic; rst : in std_logic; d : in std_logic; lock : out std_logic; clock_out : out std_logic); end clockdll_design;
architecture arch of clockdll_design is
component CLKDLL port( CLKIN : in STD_LOGIC; CLKFB : in STD_LOGIC; RST : in STD_LOGIC; CLK0 : out STD_LOGIC; CLK90 : out STD_LOGIC; CLK180 : out STD_LOGIC; CLK270 : out STD_LOGIC; CLK2X : out STD_LOGIC; CLKDV : out STD_LOGIC; LOCKED : out STD_LOGIC); end component;
component BUFG port(i : in std_logic; o : out std_logic); end component;
component IBUFG port(i : in std_logic; o : out std_logic); end component;
signal clock_0 : std_logic; signal feed_back : std_logic; signal clk_in_dll : std_logic;