General Description: Known Issues in the C_IP5 IP Update
ソリューション
VHDL Simulation Analyze Order: --------------------------------------------------- (Xilinx Solution #6250) has been updated to indicate the order in which the VHDL behavioral simulation models must be analyzed for this release.
KNOWN ISSUES:
General: ------------- 1) 3.1i, 2.1i MAP: Inputs incorrectly initialized to 1 instead of 0 in backannotated timing simulation. Applies to Virtex Accumulator, Adder/Subtracter, and FD-based Register cores Reference: (Xilinx Answer #9132)
2) 2.1i COREGEN: Main core customization GUI can be closed while Register Options box remains open. Reference: (Xilinx Answer #6148)
DA FIR Core -------------------- 1) COREGEN - Internal error: "FATAL: Sim SCALING_ACCUM: equateNets failed " when generating the Virtex DA FIR Filter Reference: (Xilinx Answer #9216)
2) COREGEN - DA FIR V2.0: "FATAL: ==> General JAVA throw caught for product <ImpNetlist>." during core generation Reference: (Xilinx Answer #9075)
3) C_IP5, Distributed Arithmetic FIR Filter, VERILOG - "** Warning: Failed to open file D:lab4_xxxx.mif for reading" Reference: (Xilinx Answer #9267)
Single Port Block RAM ------------------------------------- Selecting "Falling_Edge" for the clock polarity from the GUI will still give you core with "Rising_Edge". Reference: (Xilinx Answer #9559)