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AR# 9182

3.1i Foundation ISE- How do I create a post place-and-route timing simulation (time_sim) file?


Keywords: FISE, Project Navigator, process, Timing Simulation, time_sim.vhd, time_sim.v, ngd_vhd, ngd_ver, SDF

Urgency: Standard

General Description:
How can I create a post place-and-route timing simulation (time_sim) file in Foundation ISE?



All Foundation ISE Processes are dependent upon the selected source; the Timing Simulation Process is dependent upon a Test Bench or Test Fixture.

By adding a Test Bench or Test Fixture to the project and selecting the Test Bench or Test Fixture, the Functional and Timing Simulation Processes are made available in the "Processes for Current Source" window.

By double-clicking "Simulate Post-Route VHDL/Verilog Model" in the "Processes for Current Source" window, the design will run through implementation, and a time_sim.vhd/time_sim.v will be created in the project directory along with an SDF file.


To create a timing simulation netlist (time_sim.edf), or to manually create a timing simulation file through the use of command lines, please see the Development System Reference Guide at:

Specifically, refer to Chapters 18-21, which address the NGDANNO, NGD2VER, NGD2VHDL, and NGD2EDIF commands.
AR# 9182
日付 09/09/2002
ステータス アーカイブ
種類 一般