AR# 9261: 3.1i COREGEN, VERILOG, MTI - # ** Warning: Failed to open file C:<dirname1><dirname2><module_name>.mif for reading during Block RAM simulation
3.1i COREGEN, VERILOG, MTI - # ** Warning: Failed to open file C:<dirname1><dirname2><module_name>.mif for reading during Block RAM simulation
When creating a "Dual Port Block Memory" core and specifying a Verilog flow, the simulation instantiation block in the VEO template includes a path to the MIF file which is to be loaded to initialize the RAM during Verilog simulation. When the core is generated on a PC, a Path may look like the following:
The file is not successfully loaded by the simulator because in Verilog, a back-slash is interpreted as an escape character that means that the next letter should be taken as a literal. As a result, the simulator cannot find this file and issues a warning,which looks like the following:
# ** Warning: Failed to open file D:lab4_coregencoregencore32x16.mif for reading : D:/CAE_tools/model_tech_5.3d_XE/win32xoem/ ../xilinx/verilog/src/corelib.v(6591)
As a result, the RAM fails to initialize.
Manually modify the path to the MIF file in the VEO file module declaration, replacing the backslashes with forward slashes, and re-instantiate the core in your HDL design then recompile and resimulate.