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AR# 9329

3.1i COREGen, ModelSim (MTI,MXE) - How do I use the VHO and configuration statement to simulate a CORE Generator Module in MTI (VHDL)?

説明

Keywords: COREGen, CORE Generator, MTI, ModelSim, simulate, instantiate, .vho, VHO, configuration

Urgency: Standard

General Description:
What are all the steps I need to follow to functionally simulate my CORE
Generator Module in MTI using VHDL?

ソリューション

1

VHDL:

1. Make sure you have the XilinxCoreLib library compiled and mapped. (See
(Xilinx Solution 8066) for instructions.)

2. Declare and instantiate your COREGen Module, using the templates in the .vho
file.

3. Copy the configuration statement from the .vho file to the same level on which your
component is instantiated. Insert the configuration snippet inside the configuration
statement as shown. An example is included below:

configuration <cfg_my_design> of <my_design> is
for <my_arch_name>
<Insert CONFIGURATION Declaration here>
end for;
end <cfg_my_design>;

NOTES: <cfg_my_design> is whatever name you want to give the configuration.
<my_arch_name> is the name of the current level architecture.
<my_design> is the entity name of the current level.

4. If this is not the top level of your design, use the other configuration template
in the .vho file, and place it on every level up to the top level of your design. This
statement is needed on every level of hierarchy.

configuration <cfg> of <next_level> is
for <arch_name>
for all : <my_design> use configuration work.<cfg_my_design>;
end for;
end for;
end <cfg>;

NOTES: <cfg> is whatever name you want to give it.
<next_level> is the current level entity.
<arch_name> is the current level architecture.
<my_design> is the entity one level down in hierarchy.
<cfg_my_design> is the name of the configuration statement one level
down.

5. Compile the design. You will receive unbound warnings from your COREGen
components. You can safely ignore these, as the configuration statement takes
care of the definition.

6. When loading the design, choose the configuration name from the top level of your
design to load. It will be of type "Config".

7. Simulate as normal.

2

VHDL EXAMPLE:

library IEEE;
use IEEE.std_logic_1164.all;

entity ramAB256x8 is
port (
ram_addr: in STD_LOGIC_VECTOR (7 downto 0);
rw: in STD_LOGIC;
cs1: in STD_LOGIC;
cs2: in STD_LOGIC;
tbuf_RAM: IN STD_LOGIC;
romram_en: in STD_LOGIC;
clk: in STD_LOGIC;
data: inout STD_LOGIC_VECTOR (7 downto 0)
);
end ramAB256x8;

architecture structural of ramAB256x8 is

-- COREGEN MODULE DECLARATION
component ram256x8
port (
a: IN std_logic_VECTOR(7 downto 0);
d: IN std_logic_VECTOR(7 downto 0);
we: IN std_logic;
c: IN std_logic;
ce: IN std_logic;
q: OUT std_logic_VECTOR(7 downto 0));
end component;

(signal declarations)

begin

-- COREGEN MODULE INSTANTIATION
RAMA: ram256x8 port map (
a => ram_addr,
d => data,
we => weA,
c => clk,
ce => ramA_en,
q => qA);

... (logic)

end structural;

-- synopsys translate_off
-- CONFIGURATION STATEMENT

Library XilinxCoreLib;

configuration cfg_ramAB256x8 of ramAB256x8 is
for structural
for all : ram256x8 use entity XilinxCoreLib.syncramVHT(behavioral)
end for;
end for;
end cfg_ramAB256x8;

-- synopsys translate_on

*********************************************************************************
ONE LEVEL UP IN HIERARCHY:
- Entity name is top
- Architecture name is top_arch

configuration cfg_top of top is
for top_arch
for all : ramAB256x8 use configuration work.cfg_ramAB256x8;
end for;
end for;
end top_cfg;
AR# 9329
作成日 08/31/2007
最終更新日 09/05/2002
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