------- MYLABEL : for i in 0 to 3 generate begin myinst : mymem port map ( <put listing of ports here> ); end generate;
: : : end myarch; ---------
この場合のコンフィギュレーションは次のとおりです。 for myarch -- the architecture name for MYLABEL -- the generate loop label for all : mymem use entity XilinxCoreLib.<coregen_behavioral_model_name>(behavioral) generic map ( <list of core parameters mapped to their values from VHO snippet> ); end for; end for; end for; ----------