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AR# 9367

3.1i Modular PAR - ERROR:Place:982 - Partially placed macro containing slice ...

説明

Keywords: Area, range, constraints, modular, active, module

General Description: A case has been seen where a design fails
during placement in the Active Module mode with the errors:

ERROR:Place:982 - Partially placed macro containing slice
vramct1/addr1/un7_rRowA_s_1 could not be placed. Please
either fix the
constraints on this macro or remove them.
ERROR:Place:982 - Partially placed macro containing slice
vramct1/addr1/un1_wColA_s_4 could not be placed. Please
either fix the constraints on this macro or remove them.

This problem is being caused by a problem in the Virtex placer
Edge/pseudo logic elements, with their location constraints, are
also being looked into by the range-constraint handler in the
analytical-placer. It should just ignore it since these elements
are handled by the IO placer and not the analytical placement part.

This problem will occur whenever a module boundary is at the chip
edge and there is significant pseudo-logic requirement.

ソリューション

This problem will be fixed in the first quarterly update to 3.1i
currently scheduled for August, 2000.
AR# 9367
作成日 05/25/2000
最終更新日 08/19/2002
ステータス アーカイブ
タイプ 一般