library IEEE; use IEEE.std_logic_1164.all; entity LVDSIO is port (CLK, DATA, Tin : in STD_LOGIC; IODATA_p, IODATA_n : inout STD_LOGIC; Q_p, Q_n : out STD_LOGIC ); end LVDSIO;
architecture BEHAV of LVDSIO is
component IBUF_LVDS is port (I : in STD_LOGIC; O : out STD_LOGIC); end component;
component OBUF_LVDS is port (I : in STD_LOGIC; O : out STD_LOGIC); end component;
component IOBUF_LVDS is port (I : in STD_LOGIC; T : in STD_LOGIC; IO : inout STD_LOGIC; O : out STD_LOGIC); end component;
component INV is port (I : in STD_LOGIC; O : out STD_LOGIC); end component;
component IBUFG_LVDS is port(I : in STD_LOGIC; O : out STD_LOGIC); end component;
component BUFG is port(I : in STD_LOGIC; O : out STD_LOGIC); end component;
signal iodata_in : std_logic; signal iodata_n_out: std_logic; signal iodata_out: std_logic; signal DATA_int : std_logic; signal Q_p_int : std_logic; signal Q_n_int : std_logic; signal CLK_int : std_logic; signal CLK_ibufgout : std_logic; signal Tin_int : std_logic;
begin UI1: IBUF_LVDS port map ( I => DATA, O => DATA_int); UI2: IBUF_LVDS port map (I => Tin, O => Tin_int); UO_p: OBUF_LVDS port map ( I => Q_p_int, O => Q_p); UO_n: OBUF_LVDS port map ( I => Q_n_int, O => Q_n); UIO_p: IOBUF_LVDS port map ( I => iodata_out, T => Tin_int, IO => iodata_p, O => iodata_in); UIO_n: IOBUF_LVDS port map ( I => iodata_n_out, T => Tin_int, IO => iodata_n, O => open);
UINV: INV port map ( I => iodata_out, O => iodata_n_out); UIBUFG : IBUFG_LVDS port map ( I => CLK, O => CLK_ibufgout); UBUFG : BUFG port map (I => CLK_ibufgout, O => CLK_int);
My_D_Reg: process (CLK_int, DATA_int) begin if (CLK_int'event and CLK_int='1') then Q_p_int <= DATA_int; end if; end process; -- End My_D_Reg
always @ (posedge CLK_int) begin Q_p_int <= DATA_int; end
assign iodata_out = DATA_int && iodata_in;
assign Q_n_int = ~Q_p_int;
endmodule
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V50ECS144 をターゲットとした UCF 構文例
NET CLK LOC = A6; #GCLK3 NET DATA LOC = A4; #IO_L0P_YY NET Q_p LOC = A5; #IO_L1P_YY NET Q_n LOC = B5; #IO_L1N_YY NET iodata_p LOC = D8; #IO_L3P_yy NET iodata_n LOC = C8; #IO_L3N_yy NET Tin LOC = F13; #IO_L10P